From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 768F738930E8 for ; Thu, 23 Jun 2022 02:02:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 768F738930E8 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25N1CgCO020299; Thu, 23 Jun 2022 02:02:57 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3gveaeryej-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Jun 2022 02:02:57 +0000 Received: from m0098396.ppops.net (m0098396.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 25N1puFP030778; Thu, 23 Jun 2022 02:02:56 GMT Received: from ppma01fra.de.ibm.com (46.49.7a9f.ip4.static.sl-reverse.com [159.122.73.70]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3gveaerydr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Jun 2022 02:02:56 +0000 Received: from pps.filterd (ppma01fra.de.ibm.com [127.0.0.1]) by ppma01fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 25N1ZdDD023464; Thu, 23 Jun 2022 02:02:54 GMT Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by ppma01fra.de.ibm.com with ESMTP id 3gv3j68kkv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Jun 2022 02:02:54 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 25N22pSl22741440 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 23 Jun 2022 02:02:51 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D89AEA4059; Thu, 23 Jun 2022 02:02:51 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5B5FBA4053; Thu, 23 Jun 2022 02:02:50 +0000 (GMT) Received: from [9.197.246.188] (unknown [9.197.246.188]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 23 Jun 2022 02:02:50 +0000 (GMT) Message-ID: <98505e00-5e91-a533-1f8e-ac1412939923@linux.ibm.com> Date: Thu, 23 Jun 2022 10:02:49 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: PING^2 [PATCH v3] rs6000: Adjust mov optabs for opaque modes [PR103353] Content-Language: en-US To: GCC Patches Cc: Peter Bergner , Segher Boessenkool , David Edelsohn References: <09c34b29-feea-d26e-2c4f-5e096ab286bc@linux.ibm.com> From: "Kewen.Lin" In-Reply-To: Content-Type: text/plain; charset=UTF-8 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 2JFVoNuaQfxkT74QUXamXZcvRNNMc-WF X-Proofpoint-ORIG-GUID: eWMtYG5Qa65-zBrs6zc9Haip5DFNaW77 Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-06-22_10,2022-06-22_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 spamscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206230005 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Jun 2022 02:03:00 -0000 Hi, Gentle ping https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595209.html BR, Kewen >> Hi, >> >> As PR103353 shows, we may want to continue to expand a MMA built-in >> function like a normal function, even if we have already emitted >> error messages about some missing required conditions. As shown in >> that PR, without one explicit mov optab on OOmode provided, it would >> call emit_move_insn recursively. >> >> So this patch is to allow the mov pattern to be generated when we are >> expanding to RTL and have seen errors even without MMA supported, it's >> expected that the generated pattern would not cause further ICEs as the >> compilation would stop soon after expanding. >> >> Bootstrapped and regtested on powerpc64-linux-gnu P8 and >> powerpc64le-linux-gnu P9 and P10. >> >> v3: Update test case with dg-excess-errors. >> >> v2: Polish some comments and add one test case as Will and Peter suggested. >> https://gcc.gnu.org/pipermail/gcc-patches/2022-April/592916.html >> >> v1: https://gcc.gnu.org/pipermail/gcc-patches/2022-March/591150.html >> >> Is it ok for trunk? >> >> BR, >> Kewen >> ----- >> PR target/103353 >> >> gcc/ChangeLog: >> >> * config/rs6000/mma.md (define_expand movoo): Move TARGET_MMA condition >> check to preparation statements and add handlings for !TARGET_MMA. >> (define_expand movxo): Likewise. >> >> gcc/testsuite/ChangeLog: >> >> * gcc.target/powerpc/pr103353.c: New test. >> --- >> gcc/config/rs6000/mma.md | 42 ++++++++++++++++++--- >> gcc/testsuite/gcc.target/powerpc/pr103353.c | 22 +++++++++++ >> 2 files changed, 58 insertions(+), 6 deletions(-) >> create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103353.c >> >> diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md >> index 907c9d6d516..746a77a0957 100644 >> --- a/gcc/config/rs6000/mma.md >> +++ b/gcc/config/rs6000/mma.md >> @@ -268,10 +268,25 @@ (define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "pmxvi8ger4pp") >> (define_expand "movoo" >> [(set (match_operand:OO 0 "nonimmediate_operand") >> (match_operand:OO 1 "input_operand"))] >> - "TARGET_MMA" >> + "" >> { >> - rs6000_emit_move (operands[0], operands[1], OOmode); >> - DONE; >> + if (TARGET_MMA) { >> + rs6000_emit_move (operands[0], operands[1], OOmode); >> + DONE; >> + } >> + /* Opaque modes are only expected to be available when MMA is supported, >> + but PR103353 shows we may want to continue to expand a MMA built-in >> + function, even if we have already emitted error messages about some >> + missing required conditions. As shown in that PR, without one >> + explicit mov optab on OOmode provided, it would call emit_move_insn >> + recursively. So we allow this pattern to be generated when we are >> + expanding to RTL and have seen errors, even though there is no MMA >> + support. It would not cause further ICEs as the compilation would >> + stop soon after expanding. */ >> + else if (currently_expanding_to_rtl && seen_error ()) >> + ; >> + else >> + gcc_unreachable (); >> }) >> >> (define_insn_and_split "*movoo" >> @@ -300,10 +315,25 @@ (define_insn_and_split "*movoo" >> (define_expand "movxo" >> [(set (match_operand:XO 0 "nonimmediate_operand") >> (match_operand:XO 1 "input_operand"))] >> - "TARGET_MMA" >> + "" >> { >> - rs6000_emit_move (operands[0], operands[1], XOmode); >> - DONE; >> + if (TARGET_MMA) { >> + rs6000_emit_move (operands[0], operands[1], XOmode); >> + DONE; >> + } >> + /* Opaque modes are only expected to be available when MMA is supported, >> + but PR103353 shows we may want to continue to expand a MMA built-in >> + function, even if we have already emitted error messages about some >> + missing required conditions. As shown in that PR, without one >> + explicit mov optab on XOmode provided, it would call emit_move_insn >> + recursively. So we allow this pattern to be generated when we are >> + expanding to RTL and have seen errors, even though there is no MMA >> + support. It would not cause further ICEs as the compilation would >> + stop soon after expanding. */ >> + else if (currently_expanding_to_rtl && seen_error ()) >> + ; >> + else >> + gcc_unreachable (); >> }) >> >> (define_insn_and_split "*movxo" >> diff --git a/gcc/testsuite/gcc.target/powerpc/pr103353.c b/gcc/testsuite/gcc.target/powerpc/pr103353.c >> new file mode 100644 >> index 00000000000..5d519fb1b7b >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/powerpc/pr103353.c >> @@ -0,0 +1,22 @@ >> +/* { dg-require-effective-target powerpc_altivec_ok } */ >> +/* If the default cpu type is power10 or later, MMA is enabled by default. >> + To keep the test point available all the time, this case specifies >> + -mdejagnu-cpu=power6 to make it be tested without MMA. */ >> +/* { dg-options "-maltivec -mdejagnu-cpu=power6" } */ >> + >> +/* Verify there is no ICE and don't check the error messages on MMA >> + requirement since they could be fragile and are not test points >> + of this case. */ >> +/* { dg-excess-errors "pr103353" } */ >> + >> +void >> +foo (__vector_pair *dst, double *x) >> +{ >> + dst[0] = __builtin_vsx_lxvp (0, (__vector_pair *)(void *)x); >> +} >> + >> +void >> +bar (__vector_pair *src, double *x) >> +{ >> + __builtin_vsx_stxvp (src[0], 0, (__vector_pair *)(void *)x); >> +} >