[PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Edwin Lu]

Updates autovec instruction that was added after last patch and turns on the
assert statement to ensure all new instructions have a type.

	* config/riscv/autovec-opt.md: Update type
	* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
 gcc/config/riscv/autovec-opt.md | 3 ++-
 gcc/config/riscv/riscv.cc       | 2 --
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 58e80044f1e..f1d058ce911 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -649,7 +649,8 @@ (define_insn_and_split "*cond_<optab><mode>"
                gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine vlmax neg and UNSPEC_VCOPYSIGN
 (define_insn_and_split "*copysign<mode>_neg"
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 12926b206ac..d3b09543ba0 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7708,11 +7708,9 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
   if (get_attr_type (insn) == TYPE_GHOST)
     return 0;
 
-#if 0
   /* If we ever encounter an insn with an unknown type, trip
      an assert so we can find and fix this problem.  */
   gcc_assert (get_attr_type (insn) != TYPE_UNKNOWN);
-#endif
 
   return more - 1;
 }
-- 
2.34.1

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Jeff Law]

On 9/11/23 16:52, Edwin Lu wrote:
> Updates autovec instruction that was added after last patch and turns on the
> assert statement to ensure all new instructions have a type.
> 
> 	* config/riscv/autovec-opt.md: Update type
> 	* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
"Remove assert" -> "Enable assert."  We're removing the #if 0 guard, not 
the assert itself :-)

OK with the ChangeLog fixed.
jeff

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Lehua Ding]

Hi Edwin,

Sorry to bother you. I have a small question for you.

On 2023/9/12 6:52, Edwin Lu wrote:
> --- a/gcc/config/riscv/autovec-opt.md +++ 
> b/gcc/config/riscv/autovec-opt.md @@ -649,7 +649,8 @@ 
> (define_insn_and_split "*cond_<optab><mode>" gen_int_mode 
> (GET_MODE_NUNITS (<MODE>mode), Pmode)}; 
> riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} 
> +[(set_attr "type" "vector")])

Is it necessary to add type attribute to these INSNs that exist only 
before split1 pass? These instructions are expanded into the pattern in 
vector.md after split1 pass and do not reach the sched1 pass at all. If 
so, I feel that these patterns cannot be added, and it is reasonable to 
report an error if these INSNs reach sched1 pass. Thanks.

-- 
Best,
Lehua

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Jeff Law]

On 9/11/23 20:33, Lehua Ding wrote:
> Hi Edwin,
> 
> Sorry to bother you. I have a small question for you.
> 
> On 2023/9/12 6:52, Edwin Lu wrote:
>> --- a/gcc/config/riscv/autovec-opt.md +++ 
>> b/gcc/config/riscv/autovec-opt.md @@ -649,7 +649,8 @@ 
>> (define_insn_and_split "*cond_<optab><mode>" gen_int_mode 
>> (GET_MODE_NUNITS (<MODE>mode), Pmode)}; 
>> riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} 
>> +[(set_attr "type" "vector")])
> 
> Is it necessary to add type attribute to these INSNs that exist only 
> before split1 pass? These instructions are expanded into the pattern in 
> vector.md after split1 pass and do not reach the sched1 pass at all. If 
> so, I feel that these patterns cannot be added, and it is reasonable to 
> report an error if these INSNs reach sched1 pass. Thanks.
I'd rather be consistent and make it policy that every insn has a type.

The next thing I'd like to do (and it's probably much more work) is to 
validate that every insn type maps to a functional unit for the sched2 
pass.  The scheduler will do some horrible things to the generated code 
when lots of insns either don't have types or the types aren't matched 
to a functional unit.

Jeff

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Lehua Ding]

Hi Jeff,

On 2023/9/12 11:00, Jeff Law wrote:
> I'd rather be consistent and make it policy that every insn has a type.

Since the type set here will not be used by sched pass (these insn 
pattern will not exit at shced pass since use define_insn_and_split with 
condition `TARGET_VECTOR && can_create_pseudo_p ()`), I think it is easy 
to cause misunderstanding and some problems are not easy to find (e.g. 
accidentally went through the sched pass should be assert error). In my 
opinion, assert in sched function can ensure that all insn pattern that 
reach sched pass have a type attribute. If not, it is a problem and 
needs to be located and checked. All insn patterns add type to allow 
assert to pass, but at the same time hide or ignore some problems. I 
don't know if there is a problem with my understanding, thank you.

-- 
Best,
Lehua

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Jeff Law]

On 9/11/23 21:17, Lehua Ding wrote:
> Hi Jeff,
> 
> On 2023/9/12 11:00, Jeff Law wrote:
>> I'd rather be consistent and make it policy that every insn has a type.
> 
> Since the type set here will not be used by sched pass (these insn 
> pattern will not exit at shced pass since use define_insn_and_split with 
> condition `TARGET_VECTOR && can_create_pseudo_p ()`), I think it is easy 
> to cause misunderstanding and some problems are not easy to find (e.g. 
> accidentally went through the sched pass should be assert error).
But that condition is _not_ generally sufficient to prevent these insns 
from existing during sched1.  ie, a pass between split1 and sched1 could 
create these patterns and successfully match them.  That in turn would 
trigger the assertion.

can_create_pseudo_p is true up through the register allocator.  As a 
result a condition like TARGET_VECTOR && can_create_pseudo_p() is _not_ 
sufficient to ensure the pattern does not exist during sched1.  While no 
pass likely creates these kinds of insns right now in that window 
between split1 and sched1, there's no guarantee that will always be true.

The simple rule is easy to follow.  Every insn should have a type.  That 
also gives us a degree of future-proof, even if someone adds additional 
passes/capabilities between split1 and sched1.


jeff

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Lehua Ding]

Hi Jeff,

On 2023/9/12 11:47, Jeff Law wrote:
> But that condition is _not_ generally sufficient to prevent these insns 
> from existing during sched1.  ie, a pass between split1 and sched1 could 
> create these patterns and successfully match them.  That in turn would 
> trigger the assertion.
> 
> can_create_pseudo_p is true up through the register allocator.  As a 
> result a condition like TARGET_VECTOR && can_create_pseudo_p() is _not_ 
> sufficient to ensure the pattern does not exist during sched1.  While no 
> pass likely creates these kinds of insns right now in that window 
> between split1 and sched1, there's no guarantee that will always be true.

But if a pass between split1 and sched1 creates these patterns, then an 
unrecognized error will throw after reload. Is that right? That is to 
say, this insn patterns is designed to exist only before split1, but now 
the conditions are a little looser, a little tighter is better if we 
can. If this is the case, I feel it makes no difference whether the 
error is thrwoed by sched pass or a pass after reload.

> The simple rule is easy to follow.  Every insn should have a type.  That 
> also gives us a degree of future-proof, even if someone adds additional 
> passes/capabilities between split1 and sched1.

However, adding content that you don't need feels even more difficult to 
understand, and this is just my feeling. It would be clearer if we could 
set the type according to the purpose of the insn pattern.

-- 
Best,
Lehua

Re: [Committed] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Edwin Lu]

On 9/11/2023 5:49 PM, Jeff Law via Gcc-patches wrote:
> 
> 
> On 9/11/23 16:52, Edwin Lu wrote:
>> Updates autovec instruction that was added after last patch and turns 
>> on the
>> assert statement to ensure all new instructions have a type.
>>
>>     * config/riscv/autovec-opt.md: Update type
>>     * config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
> "Remove assert" -> "Enable assert."  We're removing the #if 0 guard, not 
> the assert itself :-)
> 
> OK with the ChangeLog fixed.
> jeff
> 
Forgot to update but committed.

Edwin

Re: [Committed] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Edwin Lu]

On 9/11/2023 5:49 PM, Jeff Law via Gcc-patches wrote:
> 
> 
> On 9/11/23 16:52, Edwin Lu wrote:
>> Updates autovec instruction that was added after last patch and turns 
>> on the
>> assert statement to ensure all new instructions have a type.
>>
>>     * config/riscv/autovec-opt.md: Update type
>>     * config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
> "Remove assert" -> "Enable assert."  We're removing the #if 0 guard, not 
> the assert itself :-)
> 
> OK with the ChangeLog fixed.
> jeff
> 
Forgot to update but committed.

Edwin

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Jeff Law]

On 9/12/23 00:18, Lehua Ding wrote:
> Hi Jeff,
> 
> On 2023/9/12 11:47, Jeff Law wrote:
>> But that condition is _not_ generally sufficient to prevent these 
>> insns from existing during sched1.  ie, a pass between split1 and 
>> sched1 could create these patterns and successfully match them.  That 
>> in turn would trigger the assertion.
>>
>> can_create_pseudo_p is true up through the register allocator.  As a 
>> result a condition like TARGET_VECTOR && can_create_pseudo_p() is 
>> _not_ sufficient to ensure the pattern does not exist during sched1.  
>> While no pass likely creates these kinds of insns right now in that 
>> window between split1 and sched1, there's no guarantee that will 
>> always be true.
> 
> But if a pass between split1 and sched1 creates these patterns, then an 
> unrecognized error will throw after reload. Is that right? That is to 
> say, this insn patterns is designed to exist only before split1, but now 
> the conditions are a little looser, a little tighter is better if we 
> can. If this is the case, I feel it makes no difference whether the 
> error is thrwoed by sched pass or a pass after reload.
If someone was to create one of these patterns without an associated 
insn type, then the assert would trigger during sched1, and that is 
good.  The earlier we can catch an inconsistency, the better.



> 
>> The simple rule is easy to follow.  Every insn should have a type.  
>> That also gives us a degree of future-proof, even if someone adds 
>> additional passes/capabilities between split1 and sched1.
> 
> However, adding content that you don't need feels even more difficult to 
> understand, and this is just my feeling. It would be clearer if we could 
> set the type according to the purpose of the insn pattern.
I understand your position, but respectfully disagree with the 
conclusion in this case.

jeff

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Lehua Ding]

Hi Jeff,

Thank you for your comments, I'm not fully convinced yet but I will 
follow the current rules. I won't dwell on this for now.

-- 
Best,
Lehua

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Jeff Law]

On 9/18/23 01:29, Lehua Ding wrote:
> Hi Jeff,
> 
> Thank you for your comments, I'm not fully convinced yet but I will 
> follow the current rules. I won't dwell on this for now.
Sounds reasonable.  Of all the things we need to do, this isn't that big :-)

jeff