[PATCH] SSE5 bug fixes

[PATCH] SSE5 bug fixes

[rajagopal, dwarak]

[-- Attachment #1: Type: text/plain, Size: 355 bytes --]

This patch fixes issues with pcmov and com* instruction generation,
which were found out by testing the compiler with spec2006 benchmarks on
SIMNOW simulator (http://developer.amd.com/simnow.jsp). After this
patch, the compiler now builds and runs spec 2006 benchmarks fine with
-msse5.

Bootstrapped on x86_64.

Is this ok?

Thanks,
- Dwarak

[-- Attachment #2: Changelog-sse5-bugfix --]
[-- Type: application/octet-stream, Size: 474 bytes --]

2007-11-12  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
	    Michael Meissner  <michael.meissner@amd.com> 

	* config/i386/i386.md (sse5_setcc<mode>): Use <ssemodefsuffix> to 
	get the appropriate suffix for the coms* instruction.
	(*sse5_pcmov_<mode>): Restrict operands of pcmov 
	for scalar case to be only xmm registers and not memory.

	* config/i386/sse.md (sse5_pcmov_<mode>): Correct the operand 
	constraints to follow the mnemonics for the pcmov instruction

[-- Attachment #3: sse5-bugfix.patch --]
[-- Type: application/octet-stream, Size: 2788 bytes --]

diff -purNw trunk/gcc/config/i386/i386.md trunk-sse5_bugfix/gcc/config/i386/i386.md
--- trunk/gcc/config/i386/i386.md	2007-11-08 13:32:31.831989000 -0600
+++ trunk-sse5_bugfix/gcc/config/i386/i386.md	2007-11-09 15:20:01.968292000 -0600
@@ -14112,7 +14112,7 @@
 	  [(match_operand:MODEF 2 "register_operand" "x")
 	   (match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
   "TARGET_SSE5"
-  "com%Y1ss\t{%3, %2, %0|%0, %2, %3}"
+  "com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "sse4arg")
    (set_attr "mode" "<MODE>")])
 
@@ -19738,13 +19738,16 @@
   [(set_attr "type" "fcmov")
    (set_attr "mode" "XF")])
 
+;; All moves in SSE5 pcmov instructions are 128 bits and hence we restrict
+;; the scalar versions to have only XMM registers as operands.
+
 ;; SSE5 conditional move
 (define_insn "*sse5_pcmov_<mode>"
-  [(set (match_operand:MODEF 0 "register_operand" "=x,x,x,x")
+  [(set (match_operand:MODEF 0 "register_operand" "=x,x")
 	(if_then_else:MODEF
-	  (match_operand:MODEF 1 "nonimmediate_operand" "xm,x,0,0")
-	  (match_operand:MODEF 2 "nonimmediate_operand" "0,0,x,xm")
-	  (match_operand:MODEF 3 "vector_move_operand" "x,xm,xm,x")))]
+	  (match_operand:MODEF 1 "register_operand" "x,0")
+	  (match_operand:MODEF 2 "register_operand" "0,x")
+	  (match_operand:MODEF 3 "register_operand" "x,x")))]
   "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1)"
   "pcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
   [(set_attr "type" "sse4arg")])
diff -purNw trunk/gcc/config/i386/sse.md trunk-sse5_bugfix/gcc/config/i386/sse.md
--- trunk/gcc/config/i386/sse.md	2007-11-08 13:32:33.170954000 -0600
+++ trunk-sse5_bugfix/gcc/config/i386/sse.md	2007-11-09 10:16:14.402275000 -0600
@@ -7894,15 +7894,15 @@
 (define_insn "sse5_pcmov_<mode>"
   [(set (match_operand:SSEMODE 0 "register_operand" "=x,x,x,x,x,x")
 	(if_then_else:SSEMODE
-	  (match_operand:SSEMODE 3 "nonimmediate_operand" "0,0,xm,xm,0,0")
-	  (match_operand:SSEMODE 1 "vector_move_operand" "x,xm,0,x,C,x")
-	  (match_operand:SSEMODE 2 "vector_move_operand" "xm,x,x,0,x,C")))]
+	  (match_operand:SSEMODE 3 "nonimmediate_operand" "0,0,xm,x,0,0")
+	  (match_operand:SSEMODE 1 "vector_move_operand" "x,xm,0,0,C,x")
+	  (match_operand:SSEMODE 2 "vector_move_operand" "xm,x,x,xm,x,C")))]
   "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1)"
   "@
-   pcmov\t{%3, %2, %1, %0|%3, %1, %2, %0}
-   pcmov\t{%3, %2, %1, %0|%3, %1, %2, %0}
-   pcmov\t{%3, %2, %1, %0|%3, %1, %2, %0}
-   pcmov\t{%3, %2, %1, %0|%3, %1, %2, %0}
+   pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}
+   pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}
+   pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}
+   pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}
    andps\t{%2, %0|%0, %2}
    andnps\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse4arg")])

Re: [PATCH] SSE5 bug fixes

[Uros Bizjak]

rajagopal, dwarak wrote:

> This patch fixes issues with pcmov and com* instruction generation,
> which were found out by testing the compiler with spec2006 benchmarks on
> SIMNOW simulator (http://developer.amd.com/simnow.jsp). After this
> patch, the compiler now builds and runs spec 2006 benchmarks fine with
> -msse5.
>
> Bootstrapped on x86_64.
>
> Is this ok?
>   

This is OK for mainline.

Thanks,
Uros.