From: Lehua Ding <lehua.ding@rivai.ai>
To: Edwin Lu <ewlu@rivosinc.com>, gcc-patches@gcc.gnu.org
Cc: gnu-toolchain@rivosinc.com, Jeff Law <jeffreyalaw@gmail.com>
Subject: Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert
Date: Tue, 12 Sep 2023 10:33:20 +0800 [thread overview]
Message-ID: <9F63A23D4D863426+7ccedfd0-d4fe-4e8f-b06b-fe08817eabce@rivai.ai> (raw)
In-Reply-To: <20230911225308.2275313-1-ewlu@rivosinc.com>
Hi Edwin,
Sorry to bother you. I have a small question for you.
On 2023/9/12 6:52, Edwin Lu wrote:
> --- a/gcc/config/riscv/autovec-opt.md +++
> b/gcc/config/riscv/autovec-opt.md @@ -649,7 +649,8 @@
> (define_insn_and_split "*cond_<optab><mode>" gen_int_mode
> (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +}
> +[(set_attr "type" "vector")])
Is it necessary to add type attribute to these INSNs that exist only
before split1 pass? These instructions are expanded into the pattern in
vector.md after split1 pass and do not reach the sched1 pass at all. If
so, I feel that these patterns cannot be added, and it is reasonable to
report an error if these INSNs reach sched1 pass. Thanks.
--
Best,
Lehua
next prev parent reply other threads:[~2023-09-12 2:33 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-11 22:52 Edwin Lu
2023-09-12 0:49 ` Jeff Law
2023-09-15 22:51 ` [Committed] " Edwin Lu
2023-09-15 22:51 ` Edwin Lu
2023-09-12 2:33 ` Lehua Ding [this message]
2023-09-12 3:00 ` [PATCH] " Jeff Law
2023-09-12 3:17 ` Lehua Ding
2023-09-12 3:47 ` Jeff Law
2023-09-12 6:18 ` Lehua Ding
2023-09-17 13:46 ` Jeff Law
2023-09-18 7:29 ` Lehua Ding
2023-09-19 17:23 ` Jeff Law
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