From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 0528D3858D28 for ; Tue, 11 Apr 2023 10:05:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0528D3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E01F9D75; Tue, 11 Apr 2023 03:06:11 -0700 (PDT) Received: from [10.2.78.76] (unknown [10.2.78.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 631A93F73F; Tue, 11 Apr 2023 03:05:26 -0700 (PDT) Message-ID: <9b3d5058-1110-8201-396a-84e18a6c038f@foss.arm.com> Date: Tue, 11 Apr 2023 11:05:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit Content-Language: en-GB To: juzhe.zhong@rivai.ai, Jeff Law , gcc-patches , "kito.cheng" , palmer , jakub , rguenther , richard.sandiford@arm.com References: <20230410144808.324346-1-juzhe.zhong@rivai.ai> <89f088ec-8692-01f5-0395-5a66ddf085d7@gmail.com> <47D962C7C724E3A2+20230410231445834316202@rivai.ai> From: Richard Earnshaw In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3490.5 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_MANYTO,NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 11/04/2023 10:46, Richard Sandiford via Gcc-patches wrote: > writes: >> ARM SVE has：svint8_t, svint8x2_t, svint8x3_t, svint8x4_t >> As far as I known, they don't have tuple type for partial vector. > > Yeah, there are no separate types for partial vectors, but there > are separate modes. E.g. VNx2QI is a partial vector of QIs, > with each QI stored in a 64-bit container. > > I agree with all the comments about the danger of growing the number of > modes too much. But it looks like rtx_def should be easy to rearrange. > Unless I'm missing something, there are less than 256 rtx codes at > present. So one simple option would be to make the code 8 bits and > the machine_mode 16 bits (and swap them, so that they stay well-aligned > wrt their size). > > That of course would create new problem if we want more than 256 codes > in future. But then there would be the option of a non-power-of-2 > split (12/12 or whatever). Also, it's possible to multiplex operations > into a single code by adding an extra operand, whereas it's harder to > multiplex modes. > > Thanks, > Richard The rtx code and mode are both accessed quite frequently, making them non-native machine sizes might have impact on the performance of accessing the fields.