From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 21840 invoked by alias); 5 Sep 2014 17:52:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 21830 invoked by uid 89); 5 Sep 2014 17:52:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 05 Sep 2014 17:52:09 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s85Hmc7P011357; Fri, 5 Sep 2014 10:48:38 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s85HmYox005275; Fri, 5 Sep 2014 10:48:34 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool , Peter Bergner Subject: [PATCH] rs6000: Fix for PR63187 Date: Fri, 05 Sep 2014 17:52:00 -0000 Message-Id: <9b8988aeae361606c2fb6c6065bbf03b71c11ae9.1409938405.git.segher@kernel.crashing.org> X-IsSubscribed: yes X-SW-Source: 2014-09/txt/msg00519.txt.bz2 I made a thinko in r214080. That patch makes the "andi." pattern not match for insns that can match "rlwinm", and also makes "rlwinm." not match insns that can match "andi." (and similar for "andis." and "rldicl" etc.) This ensures we always choose the cheapest instruction. However, the splitter for "andi." does not take this into account, and generates a clobber always, leading to unrecognisable instructions. This patch fixes it. Okay if it survives bootstrap+regcheck? Segher 2014-09-05 Segher Boessenkool PR target/63187 * config/rs6000/rs6000.md (*and3_imm_dot, *and3_imm_dot2): Do not allow any_mask_operand for operands[2]. (*and3_imm_mask_dot, *and3_imm_mask_dot2): New. --- gcc/config/rs6000/rs6000.md | 56 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8f3549e..2df8e41 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2736,7 +2736,8 @@ (define_insn_and_split "*and3_imm_dot" (clobber (match_scratch:GPR 0 "=r,r")) (clobber (match_scratch:CC 4 "=X,x"))] "(mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff) - && rs6000_gen_cell_microcode" + && rs6000_gen_cell_microcode + && !any_mask_operand (operands[2], mode)" "@ andi%e2. %0,%1,%u2 #" @@ -2763,7 +2764,8 @@ (define_insn_and_split "*and3_imm_dot2" (match_dup 2))) (clobber (match_scratch:CC 4 "=X,x"))] "(mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff) - && rs6000_gen_cell_microcode" + && rs6000_gen_cell_microcode + && !any_mask_operand (operands[2], mode)" "@ andi%e2. %0,%1,%u2 #" @@ -2780,6 +2782,56 @@ (define_insn_and_split "*and3_imm_dot2" (set_attr "dot" "yes") (set_attr "length" "4,8")]) +(define_insn_and_split "*and3_imm_mask_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") + (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") + (match_operand:GPR 2 "logical_const_operand" "n,n")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "(mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff) + && rs6000_gen_cell_microcode + && any_mask_operand (operands[2], mode)" + "@ + andi%e2. %0,%1,%u2 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(set (match_dup 0) + (and:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) + +(define_insn_and_split "*and3_imm_mask_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") + (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") + (match_operand:GPR 2 "logical_const_operand" "n,n")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (and:GPR (match_dup 1) + (match_dup 2)))] + "(mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff) + && rs6000_gen_cell_microcode + && any_mask_operand (operands[2], mode)" + "@ + andi%e2. %0,%1,%u2 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(set (match_dup 0) + (and:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) + (define_insn "*and3_mask" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") -- 1.8.1.4