From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 4F7433858D28 for ; Fri, 12 Aug 2022 14:19:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4F7433858D28 Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27CE5KbX040185 for ; Fri, 12 Aug 2022 14:19:28 GMT Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3hwraprg9c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 12 Aug 2022 14:19:27 +0000 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 27CE8MpX016787 for ; Fri, 12 Aug 2022 14:19:26 GMT Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by ppma03ams.nl.ibm.com with ESMTP id 3huwvg3a95-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 12 Aug 2022 14:19:25 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 27CEJMBV29753618 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 12 Aug 2022 14:19:22 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B05FB5204F; Fri, 12 Aug 2022 14:19:22 +0000 (GMT) Received: from [9.171.46.216] (unknown [9.171.46.216]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTPS id 884F25204E; Fri, 12 Aug 2022 14:19:22 +0000 (GMT) Message-ID: <9b945d49-84c5-b05a-93e6-ac8663e433ea@linux.ibm.com> Date: Fri, 12 Aug 2022 16:19:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Content-Language: en-US To: GCC Patches , Andreas Krebbel From: Robin Dapp Subject: [PATCH] s390: Implement vec_extract via vec_select. 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Therefore we can get rid of the UNSPEC_VEC_EXTRACT that was preventing further optimizations like combining instructions with vec_extract patterns. Bootstrapped and regtested. No regressions. Is it OK? Regards Robin gcc/ChangeLog: * config/s390/s390.md: Remove UNSPEC_VEC_EXTRACT. * config/s390/vector.md: Rewrite patterns to use vec_select. * config/s390/vx-builtins.md (vec_scatter_element_SI): Likewise. --- diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 55c0064bba84..f37d8fd33a15 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -153,7 +153,6 @@ (define_c_enum "unspec" [ UNSPEC_VEC_VMALO UNSPEC_VEC_GATHER - UNSPEC_VEC_EXTRACT UNSPEC_VEC_INSERT_AND_ZERO UNSPEC_VEC_LOAD_BNDRY UNSPEC_VEC_LOAD_LEN @@ -1744,8 +1743,8 @@ (define_split && GENERAL_REG_P (operands[0]) && VECTOR_REG_P (operands[1])" [(set (match_dup 2) (match_dup 4)) - (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] - UNSPEC_VEC_EXTRACT))] + (set (match_dup 3) (vec_select:DI (match_dup 5) + (parallel [(const_int 1)])))] { operands[2] = operand_subword (operands[0], 0, 0, TImode); operands[3] = operand_subword (operands[0], 1, 0, TImode); diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 6f46bed03e00..6a7ee7870f37 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -264,11 +264,13 @@ (define_split (match_operand:V_128 1 "register_operand" ""))] "TARGET_VX && GENERAL_REG_P (operands[0]) && VECTOR_REG_P (operands[1])" [(set (match_dup 2) - (unspec:DI [(subreg:V2DI (match_dup 1) 0) - (const_int 0)] UNSPEC_VEC_EXTRACT)) + (vec_select:DI + (subreg:V2DI (match_dup 1) 0) + (parallel [(const_int 0)]))) (set (match_dup 3) - (unspec:DI [(subreg:V2DI (match_dup 1) 0) - (const_int 1)] UNSPEC_VEC_EXTRACT))] + (vec_select:DI + (subreg:V2DI (match_dup 1) 0) + (parallel [(const_int 1)])))] { operands[2] = operand_subword (operands[0], 0, 0, mode); operands[3] = operand_subword (operands[0], 1, 0, mode); @@ -505,22 +507,24 @@ (define_insn "*vec_set_plus" [(set_attr "op_type" "VRS")]) -; FIXME: Support also vector mode operands for 0 -; FIXME: This should be (vec_select ..) or something but it does only allow constant selectors :( -; This is used via RTL standard name as well as for expanding the builtin +;; FIXME: Support also vector mode operands for 0 +;; This is used via RTL standard name as well as for expanding the builtin (define_expand "vec_extract" - [(set (match_operand: 0 "nonimmediate_operand" "") - (unspec: [(match_operand:V 1 "register_operand" "") - (match_operand:SI 2 "nonmemory_operand" "")] - UNSPEC_VEC_EXTRACT))] - "TARGET_VX") + [(set (match_operand: 0 "nonimmediate_operand" "") + (vec_select: + (match_operand:V 1 "register_operand" "") + (parallel + [(match_operand:SI 2 "nonmemory_operand" "")])))] + "TARGET_VX" +) ; vlgvb, vlgvh, vlgvf, vlgvg, vsteb, vsteh, vstef, vsteg (define_insn "*vec_extract" - [(set (match_operand: 0 "nonimmediate_operand" "=d,R") - (unspec: [(match_operand:V 1 "register_operand" "v,v") - (match_operand:SI 2 "nonmemory_operand" "an,I")] - UNSPEC_VEC_EXTRACT))] + [(set (match_operand: 0 "nonimmediate_operand" "=d,R") + (vec_select: + (match_operand:V 1 "nonmemory_operand" "v,v") + (parallel + [(match_operand:SI 2 "nonmemory_operand" "an,I")])))] "TARGET_VX && (!CONST_INT_P (operands[2]) || UINTVAL (operands[2]) < GET_MODE_NUNITS (mode))" @@ -531,11 +535,11 @@ (define_insn "*vec_extract" ; vlgvb, vlgvh, vlgvf, vlgvg (define_insn "*vec_extract_plus" - [(set (match_operand: 0 "nonimmediate_operand" "=d") - (unspec: [(match_operand:V 1 "register_operand" "v") - (plus:SI (match_operand:SI 2 "nonmemory_operand" "a") - (match_operand:SI 3 "const_int_operand" "n"))] - UNSPEC_VEC_EXTRACT))] + [(set (match_operand: 0 "nonimmediate_operand" "=d") + (vec_select: + (match_operand:V 1 "register_operand" "v") + (plus:SI (match_operand:SI 2 "nonmemory_operand" "a") + (parallel [(match_operand:SI 3 "const_int_operand" "n")]))))] "TARGET_VX" "vlgv\t%0,%v1,%Y3(%2)" [(set_attr "op_type" "VRS")]) diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 22d0355ec219..fc13f0a3393e 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -440,12 +440,13 @@ (define_expand "vec_splat" (define_insn "vec_scatter_element_DI" [(set (mem: (plus:DI (zero_extend:DI - (unspec:SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:QI 3 "const_mask_operand" "C")] - UNSPEC_VEC_EXTRACT)) - (match_operand:SI 2 "address_operand" "ZQ"))) - (unspec: [(match_operand:V_HW_4 0 "register_operand" "v") - (match_dup 3)] UNSPEC_VEC_EXTRACT))] + (vec_select:SI + (match_operand:V4SI 1 "register_operand" "v") + (parallel [(match_operand:QI 3 "const_mask_operand" "C")]))) + (match_operand:SI 2 "address_operand" "ZQ"))) + (vec_select: + (match_operand:V_HW_4 0 "register_operand" "v") + (parallel [(match_dup 3)])))] "TARGET_VX && TARGET_64BIT && UINTVAL (operands[3]) < 4" "vscef\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) @@ -455,12 +456,13 @@ (define_insn "vec_scatter_element_DI" (define_insn "vec_scatter_element_SI" [(set (mem: (plus:SI (subreg:SI - (unspec: [(match_operand:V_HW_2 1 "register_operand" "v") - (match_operand:QI 3 "const_mask_operand" "C")] - UNSPEC_VEC_EXTRACT) 4) - (match_operand:SI 2 "address_operand" "ZQ"))) - (unspec: [(match_operand:V_HW_2 0 "register_operand" "v") - (match_dup 3)] UNSPEC_VEC_EXTRACT))] + (vec_select: + (match_operand:V_HW_2 1 "register_operand" "v") + (parallel [(match_operand:QI 3 "const_mask_operand" "C")])) 4) + (match_operand:SI 2 "address_operand" "ZQ"))) + (vec_select: + (match_operand:V_HW_2 0 "register_operand" "v") + (parallel [(match_dup 3)])))] "TARGET_VX && !TARGET_64BIT && UINTVAL (operands[3]) < GET_MODE_NUNITS (mode)" "vsce\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) @@ -469,13 +471,14 @@ (define_insn "vec_scatter_element_SI" ; vscef, vsceg (define_insn "vec_scatter_element_" [(set (mem: - (plus: (unspec: - [(match_operand: 1 "register_operand" "v") - (match_operand:QI 3 "const_mask_operand" "C")] - UNSPEC_VEC_EXTRACT) - (match_operand:DI 2 "address_operand" "ZQ"))) - (unspec: [(match_operand:V_HW_32_64 0 "register_operand" "v") - (match_dup 3)] UNSPEC_VEC_EXTRACT))] + (plus: + (vec_select: + (match_operand: 1 "register_operand" "v") + (parallel [(match_operand:QI 3 "const_mask_operand" "C")])) + (match_operand:DI 2 "address_operand" "ZQ"))) + (vec_select: + (match_operand:V_HW_32_64 0 "register_operand" "v") + (parallel [(match_dup 3)])))] "TARGET_VX && UINTVAL (operands[3]) < GET_MODE_NUNITS (mode)" "vsce\t%v0,%O2(%v1,%R2),%3" [(set_attr "op_type" "VRV")]) @@ -1892,9 +1895,11 @@ (define_expand "vec_st2f" (const_int VEC_RND_CURRENT)] UNSPEC_VEC_VFLR)) (set (match_operand:SF 1 "memory_operand" "") - (unspec:SF [(match_dup 2) (const_int 0)] UNSPEC_VEC_EXTRACT)) + (vec_select:SF (match_dup 2) + (parallel [(const_int 0)]))) (set (match_dup 3) - (unspec:SF [(match_dup 2) (const_int 2)] UNSPEC_VEC_EXTRACT))] + (vec_select:SF (match_dup 2) + (parallel [(const_int 2)])))] "TARGET_VX" { operands[2] = gen_reg_rtx (V4SFmode); @@ -2324,10 +2329,10 @@ (define_insn "*vec_set_bswap_vec" ; *a = vec_revb (b)[1]; get-element-bswap-4.c ; vstebrh, vstebrf, vstebrg (define_insn "*vec_extract_bswap_vec" - [(set (match_operand: 0 "memory_operand" "=R") - (unspec: [(bswap:V_HW_HSD (match_operand:V_HW_HSD 1 "register_operand" "v")) - (match_operand:SI 2 "const_int_operand" "C")] - UNSPEC_VEC_EXTRACT))] + [(set (match_operand: 0 "memory_operand" "=R") + (vec_select: + (bswap:V_HW_HSD (match_operand:V_HW_HSD 1 "register_operand" "v")) + (parallel [(match_operand:SI 2 "const_int_operand" "C")])))] "TARGET_VXE2 && UINTVAL (operands[2]) < GET_MODE_NUNITS (mode)" "vstebr\t%v1,%0,%2" [(set_attr "op_type" "VRX")]) @@ -2336,11 +2341,11 @@ (define_insn "*vec_extract_bswap_vec" ; *a = __builtin_bswap32 (b[1]); get-element-bswap-2.c ; vstebrh, vstebrf, vstebrg (define_insn "*vec_extract_bswap_elem" - [(set (match_operand: 0 "memory_operand" "=R") + [(set (match_operand: 0 "memory_operand" "=R") (bswap: - (unspec: [(match_operand:V_HW_HSD 1 "register_operand" "v") - (match_operand:SI 2 "const_int_operand" "C")] - UNSPEC_VEC_EXTRACT)))] + (vec_select: + (match_operand:V_HW_HSD 1 "register_operand" "v") + (parallel [(match_operand:SI 2 "const_int_operand" "C")]))))] "TARGET_VXE2 && UINTVAL (operands[2]) < GET_MODE_NUNITS (mode)" "vstebr\t%v1,%0,%2" [(set_attr "op_type" "VRX")]) -- 2.31.1