* [PATCH 1/2] rs6000: Redo darn (PR103624)
@ 2021-12-17 17:36 Segher Boessenkool
2021-12-17 17:36 ` [PATCH 2/2] rs6000: Update darn testcases Segher Boessenkool
2021-12-17 18:20 ` [PATCH 1/2] rs6000: Redo darn (PR103624) Bill Schmidt
0 siblings, 2 replies; 4+ messages in thread
From: Segher Boessenkool @ 2021-12-17 17:36 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, wschmidt, Segher Boessenkool
The builtins now all return "long". The patterns have :GPR as the
output mode, so they can be 32-bit as well (the instruction makes sense
in 32 bit just fine). The builtins expand to the DImode version
normally, but to the SImode if {32bit} is true.
2021-12-17 Segher Boessenkool <segher@kernel.crashing.org>
PR target/103624
* config/rs6000/rs6000-builtins.def (__builtin_darn): Expand to
darn_64_di. Add {32bit} attribute. Return long.
(__builtin_darn_32): Expand to darn_32_di. Add {32bit} attribute.
Return long.
(__builtin_darn_raw): Expand to darn_raw_di. Add {32bit} attribute.
Return long.
* config/rs6000/rs6000-call.c (rs6000_expand_builtin): Expand the darn
builtins to the _si variants for -m32.
* config/rs6000/rs6000.md (UNSPECV_DARN_32, UNSPECV_DARN_RAW): Delete.
(UNSPECV_DARN): Update comment.
(darn_32, darn_raw, darn): Delete.
(darn_32_<mode>, darn_64_<mode>, darn_raw_<mode> for GPR): New.
(@darn<mode> for GPR): New.
---
gcc/config/rs6000/rs6000-builtins.def | 12 ++++-----
gcc/config/rs6000/rs6000-call.c | 6 +++++
gcc/config/rs6000/rs6000.md | 47 +++++++++++++++++++++--------------
3 files changed, 40 insertions(+), 25 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 45ce160bd421..3ad5a135eaec 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2798,14 +2798,14 @@
; Miscellaneous P9 functions
[power9]
- signed long long __builtin_darn ();
- DARN darn {}
+ signed long __builtin_darn ();
+ DARN darn_64_di {32bit}
- signed int __builtin_darn_32 ();
- DARN_32 darn_32 {}
+ signed long __builtin_darn_32 ();
+ DARN_32 darn_32_di {32bit}
- signed long long __builtin_darn_raw ();
- DARN_RAW darn_raw {}
+ signed long __builtin_darn_raw ();
+ DARN_RAW darn_raw_di {32bit}
const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64);
TSTSFI_EQ_DD dfptstsfi_eq_dd {}
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index b98f4a4c97f7..cc55174c6b72 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -5631,6 +5631,12 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
icode = CODE_FOR_rs6000_mftb_si;
else if (fcode == RS6000_BIF_BPERMD)
icode = CODE_FOR_bpermd_si;
+ else if (fcode == RS6000_BIF_DARN)
+ icode = CODE_FOR_darn_64_si;
+ else if (fcode == RS6000_BIF_DARN_32)
+ icode = CODE_FOR_darn_32_si;
+ else if (fcode == RS6000_BIF_DARN_RAW)
+ icode = CODE_FOR_darn_raw_si;
else
gcc_unreachable ();
}
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4122acb98cfd..9be484c7cf83 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -172,9 +172,7 @@ (define_c_enum "unspecv"
UNSPECV_EH_RR ; eh_reg_restore
UNSPECV_ISYNC ; isync instruction
UNSPECV_MFTB ; move from time base
- UNSPECV_DARN ; darn 1 (deliver a random number)
- UNSPECV_DARN_32 ; darn 2
- UNSPECV_DARN_RAW ; darn 0
+ UNSPECV_DARN ; darn (deliver a random number)
UNSPECV_NLGR ; non-local goto receiver
UNSPECV_MFFS ; Move from FPSCR
UNSPECV_MFFSL ; Move from FPSCR light instruction version
@@ -15065,25 +15063,36 @@ (define_insn "*cmp<mode>_hw"
\f
;; Miscellaneous ISA 3.0 (power9) instructions
-(define_insn "darn_32"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))]
+(define_expand "darn_32_<mode>"
+ [(use (match_operand:GPR 0 "register_operand"))]
"TARGET_P9_MISC"
- "darn %0,0"
- [(set_attr "type" "integer")])
+{
+ emit_insn (gen_darn (<MODE>mode, operands[0], const0_rtx));
+ DONE;
+})
-(define_insn "darn_raw"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))]
- "TARGET_P9_MISC && TARGET_64BIT"
- "darn %0,2"
- [(set_attr "type" "integer")])
+(define_expand "darn_64_<mode>"
+ [(use (match_operand:GPR 0 "register_operand"))]
+ "TARGET_P9_MISC"
+{
+ emit_insn (gen_darn (<MODE>mode, operands[0], const1_rtx));
+ DONE;
+})
-(define_insn "darn"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))]
- "TARGET_P9_MISC && TARGET_64BIT"
- "darn %0,1"
+(define_expand "darn_raw_<mode>"
+ [(use (match_operand:GPR 0 "register_operand"))]
+ "TARGET_P9_MISC"
+{
+ emit_insn (gen_darn (<MODE>mode, operands[0], const2_rtx));
+ DONE;
+})
+
+(define_insn "@darn<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (unspec_volatile:GPR [(match_operand 1 "const_int_operand" "n")]
+ UNSPECV_DARN))]
+ "TARGET_P9_MISC"
+ "darn %0,%1"
[(set_attr "type" "integer")])
;; Test byte within range.
--
1.8.3.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] rs6000: Update darn testcases
2021-12-17 17:36 [PATCH 1/2] rs6000: Redo darn (PR103624) Segher Boessenkool
@ 2021-12-17 17:36 ` Segher Boessenkool
2021-12-17 18:21 ` Bill Schmidt
2021-12-17 18:20 ` [PATCH 1/2] rs6000: Redo darn (PR103624) Bill Schmidt
1 sibling, 1 reply; 4+ messages in thread
From: Segher Boessenkool @ 2021-12-17 17:36 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, wschmidt, Segher Boessenkool
Make the darn testcases work (and be tested) in 32-bit mode as well.
They used to ICE, but they no longer do.
2021-12-17 Segher Boessenkool <segher@kernel.crashing.org>
gcc/testsuite/
PR target/103624
* gcc.target/powerpc/darn-0.c: Remove target clause.
* gcc.target/powerpc/darn-1.c: Remove target clause. Remove lp64
requirement. Change return type to long.
* gcc.target/powerpc/darn-2.c: Ditto.
* gcc.target/powerpc/darn-3.c: Remove target clause.
---
gcc/testsuite/gcc.target/powerpc/darn-0.c | 2 +-
gcc/testsuite/gcc.target/powerpc/darn-1.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/darn-2.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/darn-3.c | 2 +-
4 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/darn-0.c b/gcc/testsuite/gcc.target/powerpc/darn-0.c
index f446f494b06d..64d98f5f91d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/darn-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/darn-0.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-mdejagnu-cpu=power9" } */
diff --git a/gcc/testsuite/gcc.target/powerpc/darn-1.c b/gcc/testsuite/gcc.target/powerpc/darn-1.c
index 0938718a5ad6..f483a89862d0 100644
--- a/gcc/testsuite/gcc.target/powerpc/darn-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/darn-1.c
@@ -1,12 +1,11 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-require-effective-target lp64 } */
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-mdejagnu-cpu=power9" } */
#include <altivec.h>
-long long get_conditioned_random ()
+long get_conditioned_random ()
{
return __builtin_darn ();
}
diff --git a/gcc/testsuite/gcc.target/powerpc/darn-2.c b/gcc/testsuite/gcc.target/powerpc/darn-2.c
index 64e44b244c4b..56a9ffb677b4 100644
--- a/gcc/testsuite/gcc.target/powerpc/darn-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/darn-2.c
@@ -1,12 +1,11 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-require-effective-target lp64 } */
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-mdejagnu-cpu=power9" } */
#include <altivec.h>
-long long get_raw_random ()
+long get_raw_random ()
{
return __builtin_darn_raw ();
}
diff --git a/gcc/testsuite/gcc.target/powerpc/darn-3.c b/gcc/testsuite/gcc.target/powerpc/darn-3.c
index 477901fde70d..4c68fad80d5d 100644
--- a/gcc/testsuite/gcc.target/powerpc/darn-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/darn-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-do compile } */
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
--
1.8.3.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] rs6000: Redo darn (PR103624)
2021-12-17 17:36 [PATCH 1/2] rs6000: Redo darn (PR103624) Segher Boessenkool
2021-12-17 17:36 ` [PATCH 2/2] rs6000: Update darn testcases Segher Boessenkool
@ 2021-12-17 18:20 ` Bill Schmidt
1 sibling, 0 replies; 4+ messages in thread
From: Bill Schmidt @ 2021-12-17 18:20 UTC (permalink / raw)
To: Segher Boessenkool, gcc-patches; +Cc: dje.gcc
Hi!
On 12/17/21 11:36 AM, Segher Boessenkool wrote:
> The builtins now all return "long". The patterns have :GPR as the
> output mode, so they can be 32-bit as well (the instruction makes sense
> in 32 bit just fine). The builtins expand to the DImode version
> normally, but to the SImode if {32bit} is true.
>
> 2021-12-17 Segher Boessenkool <segher@kernel.crashing.org>
>
> PR target/103624
> * config/rs6000/rs6000-builtins.def (__builtin_darn): Expand to
> darn_64_di. Add {32bit} attribute. Return long.
> (__builtin_darn_32): Expand to darn_32_di. Add {32bit} attribute.
> Return long.
> (__builtin_darn_raw): Expand to darn_raw_di. Add {32bit} attribute.
> Return long.
> * config/rs6000/rs6000-call.c (rs6000_expand_builtin): Expand the darn
> builtins to the _si variants for -m32.
> * config/rs6000/rs6000.md (UNSPECV_DARN_32, UNSPECV_DARN_RAW): Delete.
> (UNSPECV_DARN): Update comment.
> (darn_32, darn_raw, darn): Delete.
> (darn_32_<mode>, darn_64_<mode>, darn_raw_<mode> for GPR): New.
> (@darn<mode> for GPR): New.
Patch LGTM. Thanks for doing the legwork on this!
Bill
>
> ---
> gcc/config/rs6000/rs6000-builtins.def | 12 ++++-----
> gcc/config/rs6000/rs6000-call.c | 6 +++++
> gcc/config/rs6000/rs6000.md | 47 +++++++++++++++++++++--------------
> 3 files changed, 40 insertions(+), 25 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index 45ce160bd421..3ad5a135eaec 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -2798,14 +2798,14 @@
>
> ; Miscellaneous P9 functions
> [power9]
> - signed long long __builtin_darn ();
> - DARN darn {}
> + signed long __builtin_darn ();
> + DARN darn_64_di {32bit}
>
> - signed int __builtin_darn_32 ();
> - DARN_32 darn_32 {}
> + signed long __builtin_darn_32 ();
> + DARN_32 darn_32_di {32bit}
>
> - signed long long __builtin_darn_raw ();
> - DARN_RAW darn_raw {}
> + signed long __builtin_darn_raw ();
> + DARN_RAW darn_raw_di {32bit}
>
> const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64);
> TSTSFI_EQ_DD dfptstsfi_eq_dd {}
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index b98f4a4c97f7..cc55174c6b72 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -5631,6 +5631,12 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
> icode = CODE_FOR_rs6000_mftb_si;
> else if (fcode == RS6000_BIF_BPERMD)
> icode = CODE_FOR_bpermd_si;
> + else if (fcode == RS6000_BIF_DARN)
> + icode = CODE_FOR_darn_64_si;
> + else if (fcode == RS6000_BIF_DARN_32)
> + icode = CODE_FOR_darn_32_si;
> + else if (fcode == RS6000_BIF_DARN_RAW)
> + icode = CODE_FOR_darn_raw_si;
> else
> gcc_unreachable ();
> }
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index 4122acb98cfd..9be484c7cf83 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -172,9 +172,7 @@ (define_c_enum "unspecv"
> UNSPECV_EH_RR ; eh_reg_restore
> UNSPECV_ISYNC ; isync instruction
> UNSPECV_MFTB ; move from time base
> - UNSPECV_DARN ; darn 1 (deliver a random number)
> - UNSPECV_DARN_32 ; darn 2
> - UNSPECV_DARN_RAW ; darn 0
> + UNSPECV_DARN ; darn (deliver a random number)
> UNSPECV_NLGR ; non-local goto receiver
> UNSPECV_MFFS ; Move from FPSCR
> UNSPECV_MFFSL ; Move from FPSCR light instruction version
> @@ -15065,25 +15063,36 @@ (define_insn "*cmp<mode>_hw"
> \f
> ;; Miscellaneous ISA 3.0 (power9) instructions
>
> -(define_insn "darn_32"
> - [(set (match_operand:SI 0 "register_operand" "=r")
> - (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))]
> +(define_expand "darn_32_<mode>"
> + [(use (match_operand:GPR 0 "register_operand"))]
> "TARGET_P9_MISC"
> - "darn %0,0"
> - [(set_attr "type" "integer")])
> +{
> + emit_insn (gen_darn (<MODE>mode, operands[0], const0_rtx));
> + DONE;
> +})
>
> -(define_insn "darn_raw"
> - [(set (match_operand:DI 0 "register_operand" "=r")
> - (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))]
> - "TARGET_P9_MISC && TARGET_64BIT"
> - "darn %0,2"
> - [(set_attr "type" "integer")])
> +(define_expand "darn_64_<mode>"
> + [(use (match_operand:GPR 0 "register_operand"))]
> + "TARGET_P9_MISC"
> +{
> + emit_insn (gen_darn (<MODE>mode, operands[0], const1_rtx));
> + DONE;
> +})
>
> -(define_insn "darn"
> - [(set (match_operand:DI 0 "register_operand" "=r")
> - (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))]
> - "TARGET_P9_MISC && TARGET_64BIT"
> - "darn %0,1"
> +(define_expand "darn_raw_<mode>"
> + [(use (match_operand:GPR 0 "register_operand"))]
> + "TARGET_P9_MISC"
> +{
> + emit_insn (gen_darn (<MODE>mode, operands[0], const2_rtx));
> + DONE;
> +})
> +
> +(define_insn "@darn<mode>"
> + [(set (match_operand:GPR 0 "register_operand" "=r")
> + (unspec_volatile:GPR [(match_operand 1 "const_int_operand" "n")]
> + UNSPECV_DARN))]
> + "TARGET_P9_MISC"
> + "darn %0,%1"
> [(set_attr "type" "integer")])
>
> ;; Test byte within range.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] rs6000: Update darn testcases
2021-12-17 17:36 ` [PATCH 2/2] rs6000: Update darn testcases Segher Boessenkool
@ 2021-12-17 18:21 ` Bill Schmidt
0 siblings, 0 replies; 4+ messages in thread
From: Bill Schmidt @ 2021-12-17 18:21 UTC (permalink / raw)
To: Segher Boessenkool, gcc-patches; +Cc: dje.gcc
Hi!
On 12/17/21 11:36 AM, Segher Boessenkool wrote:
> Make the darn testcases work (and be tested) in 32-bit mode as well.
> They used to ICE, but they no longer do.
>
>
> 2021-12-17 Segher Boessenkool <segher@kernel.crashing.org>
>
> gcc/testsuite/
> PR target/103624
> * gcc.target/powerpc/darn-0.c: Remove target clause.
> * gcc.target/powerpc/darn-1.c: Remove target clause. Remove lp64
> requirement. Change return type to long.
> * gcc.target/powerpc/darn-2.c: Ditto.
> * gcc.target/powerpc/darn-3.c: Remove target clause.
LGTM.
Thanks!
Bill
>
> ---
> gcc/testsuite/gcc.target/powerpc/darn-0.c | 2 +-
> gcc/testsuite/gcc.target/powerpc/darn-1.c | 5 ++---
> gcc/testsuite/gcc.target/powerpc/darn-2.c | 5 ++---
> gcc/testsuite/gcc.target/powerpc/darn-3.c | 2 +-
> 4 files changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/darn-0.c b/gcc/testsuite/gcc.target/powerpc/darn-0.c
> index f446f494b06d..64d98f5f91d7 100644
> --- a/gcc/testsuite/gcc.target/powerpc/darn-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/darn-0.c
> @@ -1,4 +1,4 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> +/* { dg-do compile } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-skip-if "" { powerpc*-*-aix* } } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/darn-1.c b/gcc/testsuite/gcc.target/powerpc/darn-1.c
> index 0938718a5ad6..f483a89862d0 100644
> --- a/gcc/testsuite/gcc.target/powerpc/darn-1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/darn-1.c
> @@ -1,12 +1,11 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> +/* { dg-do compile } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-skip-if "" { powerpc*-*-aix* } } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
>
> #include <altivec.h>
>
> -long long get_conditioned_random ()
> +long get_conditioned_random ()
> {
> return __builtin_darn ();
> }
> diff --git a/gcc/testsuite/gcc.target/powerpc/darn-2.c b/gcc/testsuite/gcc.target/powerpc/darn-2.c
> index 64e44b244c4b..56a9ffb677b4 100644
> --- a/gcc/testsuite/gcc.target/powerpc/darn-2.c
> +++ b/gcc/testsuite/gcc.target/powerpc/darn-2.c
> @@ -1,12 +1,11 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> +/* { dg-do compile } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-skip-if "" { powerpc*-*-aix* } } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
>
> #include <altivec.h>
>
> -long long get_raw_random ()
> +long get_raw_random ()
> {
> return __builtin_darn_raw ();
> }
> diff --git a/gcc/testsuite/gcc.target/powerpc/darn-3.c b/gcc/testsuite/gcc.target/powerpc/darn-3.c
> index 477901fde70d..4c68fad80d5d 100644
> --- a/gcc/testsuite/gcc.target/powerpc/darn-3.c
> +++ b/gcc/testsuite/gcc.target/powerpc/darn-3.c
> @@ -1,4 +1,4 @@
> -/* { dg-do compile { target { powerpc*-*-* } } } */
> +/* { dg-do compile } */
> /* { dg-skip-if "" { powerpc*-*-aix* } } */
> /* { dg-options "-O2 -mdejagnu-cpu=power9" } */
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2021-12-17 17:36 [PATCH 1/2] rs6000: Redo darn (PR103624) Segher Boessenkool
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2021-12-17 18:21 ` Bill Schmidt
2021-12-17 18:20 ` [PATCH 1/2] rs6000: Redo darn (PR103624) Bill Schmidt
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