From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 37E5E3858407 for ; Fri, 17 Dec 2021 18:20:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 37E5E3858407 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1BHIIRZX011798; Fri, 17 Dec 2021 18:20:54 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 3cys723eh5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Dec 2021 18:20:53 +0000 Received: from m0098404.ppops.net (m0098404.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 1BHIKr4K026683; Fri, 17 Dec 2021 18:20:53 GMT Received: from ppma01dal.us.ibm.com (83.d6.3fa9.ip4.static.sl-reverse.com [169.63.214.131]) by mx0a-001b2d01.pphosted.com with ESMTP id 3cys723egx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Dec 2021 18:20:53 +0000 Received: from pps.filterd (ppma01dal.us.ibm.com [127.0.0.1]) by ppma01dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 1BHI9iOS015489; Fri, 17 Dec 2021 18:20:52 GMT Received: from b01cxnp23032.gho.pok.ibm.com (b01cxnp23032.gho.pok.ibm.com [9.57.198.27]) by ppma01dal.us.ibm.com with ESMTP id 3cy7e56ng7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Dec 2021 18:20:52 +0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1BHIKoeF28246426 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Dec 2021 18:20:51 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C0DD9AC096; Fri, 17 Dec 2021 18:20:50 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6303FAC059; Fri, 17 Dec 2021 18:20:50 +0000 (GMT) Received: from [9.163.5.227] (unknown [9.163.5.227]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP; Fri, 17 Dec 2021 18:20:50 +0000 (GMT) Message-ID: <9c26a681-0648-2a1d-9f7d-c7b2e781f8f6@linux.ibm.com> Date: Fri, 17 Dec 2021 12:20:49 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.4.0 Reply-To: wschmidt@linux.ibm.com Subject: Re: [PATCH 1/2] rs6000: Redo darn (PR103624) To: Segher Boessenkool , gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com References: <13977b80c6a1deb0dc048f36f262cb3ec9c4d48c.1639760570.git.segher@kernel.crashing.org> From: Bill Schmidt In-Reply-To: <13977b80c6a1deb0dc048f36f262cb3ec9c4d48c.1639760570.git.segher@kernel.crashing.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: fSHRZjnNcmMBYMiS-zJsQ94vU5gJEVw7 X-Proofpoint-GUID: -4_e_9JIeXdxGSSGELVXXWn1LtR1DySv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-17_07,2021-12-16_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 clxscore=1015 mlxscore=0 bulkscore=0 suspectscore=0 phishscore=0 spamscore=0 impostorscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2112170102 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, NICE_REPLY_A, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Dec 2021 18:20:56 -0000 Hi! On 12/17/21 11:36 AM, Segher Boessenkool wrote: > The builtins now all return "long". The patterns have :GPR as the > output mode, so they can be 32-bit as well (the instruction makes sense > in 32 bit just fine). The builtins expand to the DImode version > normally, but to the SImode if {32bit} is true. > > 2021-12-17 Segher Boessenkool > > PR target/103624 > * config/rs6000/rs6000-builtins.def (__builtin_darn): Expand to > darn_64_di. Add {32bit} attribute. Return long. > (__builtin_darn_32): Expand to darn_32_di. Add {32bit} attribute. > Return long. > (__builtin_darn_raw): Expand to darn_raw_di. Add {32bit} attribute. > Return long. > * config/rs6000/rs6000-call.c (rs6000_expand_builtin): Expand the darn > builtins to the _si variants for -m32. > * config/rs6000/rs6000.md (UNSPECV_DARN_32, UNSPECV_DARN_RAW): Delete. > (UNSPECV_DARN): Update comment. > (darn_32, darn_raw, darn): Delete. > (darn_32_, darn_64_, darn_raw_ for GPR): New. > (@darn for GPR): New. Patch LGTM.  Thanks for doing the legwork on this! Bill > > --- > gcc/config/rs6000/rs6000-builtins.def | 12 ++++----- > gcc/config/rs6000/rs6000-call.c | 6 +++++ > gcc/config/rs6000/rs6000.md | 47 +++++++++++++++++++++-------------- > 3 files changed, 40 insertions(+), 25 deletions(-) > > diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def > index 45ce160bd421..3ad5a135eaec 100644 > --- a/gcc/config/rs6000/rs6000-builtins.def > +++ b/gcc/config/rs6000/rs6000-builtins.def > @@ -2798,14 +2798,14 @@ > > ; Miscellaneous P9 functions > [power9] > - signed long long __builtin_darn (); > - DARN darn {} > + signed long __builtin_darn (); > + DARN darn_64_di {32bit} > > - signed int __builtin_darn_32 (); > - DARN_32 darn_32 {} > + signed long __builtin_darn_32 (); > + DARN_32 darn_32_di {32bit} > > - signed long long __builtin_darn_raw (); > - DARN_RAW darn_raw {} > + signed long __builtin_darn_raw (); > + DARN_RAW darn_raw_di {32bit} > > const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64); > TSTSFI_EQ_DD dfptstsfi_eq_dd {} > diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c > index b98f4a4c97f7..cc55174c6b72 100644 > --- a/gcc/config/rs6000/rs6000-call.c > +++ b/gcc/config/rs6000/rs6000-call.c > @@ -5631,6 +5631,12 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, > icode = CODE_FOR_rs6000_mftb_si; > else if (fcode == RS6000_BIF_BPERMD) > icode = CODE_FOR_bpermd_si; > + else if (fcode == RS6000_BIF_DARN) > + icode = CODE_FOR_darn_64_si; > + else if (fcode == RS6000_BIF_DARN_32) > + icode = CODE_FOR_darn_32_si; > + else if (fcode == RS6000_BIF_DARN_RAW) > + icode = CODE_FOR_darn_raw_si; > else > gcc_unreachable (); > } > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md > index 4122acb98cfd..9be484c7cf83 100644 > --- a/gcc/config/rs6000/rs6000.md > +++ b/gcc/config/rs6000/rs6000.md > @@ -172,9 +172,7 @@ (define_c_enum "unspecv" > UNSPECV_EH_RR ; eh_reg_restore > UNSPECV_ISYNC ; isync instruction > UNSPECV_MFTB ; move from time base > - UNSPECV_DARN ; darn 1 (deliver a random number) > - UNSPECV_DARN_32 ; darn 2 > - UNSPECV_DARN_RAW ; darn 0 > + UNSPECV_DARN ; darn (deliver a random number) > UNSPECV_NLGR ; non-local goto receiver > UNSPECV_MFFS ; Move from FPSCR > UNSPECV_MFFSL ; Move from FPSCR light instruction version > @@ -15065,25 +15063,36 @@ (define_insn "*cmp_hw" > > ;; Miscellaneous ISA 3.0 (power9) instructions > > -(define_insn "darn_32" > - [(set (match_operand:SI 0 "register_operand" "=r") > - (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))] > +(define_expand "darn_32_" > + [(use (match_operand:GPR 0 "register_operand"))] > "TARGET_P9_MISC" > - "darn %0,0" > - [(set_attr "type" "integer")]) > +{ > + emit_insn (gen_darn (mode, operands[0], const0_rtx)); > + DONE; > +}) > > -(define_insn "darn_raw" > - [(set (match_operand:DI 0 "register_operand" "=r") > - (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))] > - "TARGET_P9_MISC && TARGET_64BIT" > - "darn %0,2" > - [(set_attr "type" "integer")]) > +(define_expand "darn_64_" > + [(use (match_operand:GPR 0 "register_operand"))] > + "TARGET_P9_MISC" > +{ > + emit_insn (gen_darn (mode, operands[0], const1_rtx)); > + DONE; > +}) > > -(define_insn "darn" > - [(set (match_operand:DI 0 "register_operand" "=r") > - (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))] > - "TARGET_P9_MISC && TARGET_64BIT" > - "darn %0,1" > +(define_expand "darn_raw_" > + [(use (match_operand:GPR 0 "register_operand"))] > + "TARGET_P9_MISC" > +{ > + emit_insn (gen_darn (mode, operands[0], const2_rtx)); > + DONE; > +}) > + > +(define_insn "@darn" > + [(set (match_operand:GPR 0 "register_operand" "=r") > + (unspec_volatile:GPR [(match_operand 1 "const_int_operand" "n")] > + UNSPECV_DARN))] > + "TARGET_P9_MISC" > + "darn %0,%1" > [(set_attr "type" "integer")]) > > ;; Test byte within range.