From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B264F3858D28 for ; Wed, 18 Jan 2023 16:41:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B264F3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84F98AD7; Wed, 18 Jan 2023 08:42:31 -0800 (PST) Received: from [10.2.78.76] (unknown [10.2.78.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9525E3F67D; Wed, 18 Jan 2023 08:41:48 -0800 (PST) Message-ID: <9d970dc5-e1a1-40c2-cbff-f790101a2210@foss.arm.com> Date: Wed, 18 Jan 2023 16:41:48 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [GCC][PATCH 13/15, v5] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature. Content-Language: en-GB To: Srinath Parvathaneni , gcc Patches Cc: Richard Earnshaw , Kyrylo Tkachov References: From: Richard Earnshaw In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3489.7 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 13/01/2023 17:44, Srinath Parvathaneni via Gcc-patches wrote: > Hello, > > This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo hard-register and also > updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directives accordingly. > This patch also adds support to emit ".pacspval" directive when "pac ip, lr, sp" instruction > in generated in the assembly. > > RA_AUTH_CODE register number is 107 and it's dwarf register number is 143. > > Applying this patch on top of PACBTI series posted here > https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599658.html and when compiling the following > test.c with "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret -mthumb -mfloat-abi=hard > fasynchronous-unwind-tables -g -O0 -S" command line options, the assembly output after this patch > looks like below: > > $cat test.c > > void fun1(int a); > void fun(int a,...) > { > fun1(a); > } > > int main() > { > fun (10); > return 0; > } > > $ arm-none-eabi-gcc -march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret -mthumb -mfloat-abi=hard > -fasynchronous-unwind-tables -g -O0 -S test.s > > Assembly output: > ... > fun: > ... > .pacspval > pac ip, lr, sp > .cfi_register 143, 12 > push {r3, r7, ip, lr} > .save {r3, r7, ra_auth_code, lr} > ... > .cfi_offset 143, -24 > ... > .cfi_restore 143 > ... > aut ip, lr, sp > bx lr > ... > main: > ... > .pacspval > pac ip, lr, sp > .cfi_register 143, 12 > push {r3, r7, ip, lr} > .save {r3, r7, ra_auth_code, lr} > ... > .cfi_offset 143, -8 > ... > .cfi_restore 143 > ... > aut ip, lr, sp > bx lr > ... > > Regression tested on arm-none-eabi target and found no regressions. > > Ok for master? > > Regards, > Srinath. > > 2023-01-11 Srinath Parvathaneni > > * config/arm/aout.h (ra_auth_code): Add entry in enum. > (emit_multi_reg_push): Add RA_AUTH_CODE register to > dwarf frame expression. > (arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register. > (arm_expand_prologue): Update frame related information and reg notes > for pac/pacbit insn. > (arm_regno_class): Check for pac pseudo reigster. > (arm_dbx_register_number): Assign ra_auth_code register number in dwarf. > (arm_init_machine_status): Set pacspval_needed to zero. > (arm_debugger_regno): Check for PAC register. > (arm_unwind_emit_sequence): Print .save directive with ra_auth_code > register. > (arm_unwind_emit_set): Add entry for IP_REGNUM in switch case. > (arm_unwind_emit): Update REG_CFA_REGISTER case._ > * config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify. > (DWARF_PAC_REGNUM): Define. > (IS_PAC_REGNUM): Likewise. > (enum reg_class): Add PAC_REG entry. > (machine_function): Add pacbti_needed state to structure. > * config/arm/arm.md (RA_AUTH_CODE): Define. > > gcc/testsuite/ChangeLog: > > 2023-01-11 Srinath Parvathaneni > > * g++.target/arm/pac-1.C: New test. > * gcc.target/arm/pac-15.c: Likewise. Your attachments are still not being correctly detected. Perhaps this is because of the filename you've chosen, which has no recognizable extension. If you name your files .patch (or .diff, or even .txt) then the system should automatically pick the right mime type for encoding. + /* NOTE: Dwarf code emitter handle reg-reg copies correctly and in the + following example reg-reg copy of SP to IP register is handled + through .cfi_def_cfa_register directive and the .cfi_offset + directive for IP register is skipped by dwarf code emitter. + Example: + mov ip, sp + .cfi_def_cfa_register 12 + push {fp, ip, lr, pc} + .cfi_offset 11, -16 + .cfi_offset 13, -12 + .cfi_offset 14, -8 + + Where as Arm-specific .save directive reg-reg copy handling is + buggy. After the reg-reg copy, the copied registers need to be It's not buggy (if it were you'd need to fix it :). It just works in a different way to the dwarf tracker and doesn't need to handle reg->reg copies. So please rephrase this. + populated in .save directive register list but with the current + implementation of .save directive original registers are getting + populated in the register list. So to avoid this issue for IP + register when PACBTI is enabled we manually updated the .save + directive register list to use "ra_auth_code" (pseduo register 143) + instead of IP register as shown in following example. + Example: + pacbti ip, lr, sp + .cfi_register 143, 12 + push {r3, r7, ip, lr} + .save {r3, r7, ra_auth_code, lr} + */ R.