[Patch, microblaze]: Adjustments to pcmp instruction generation

[Patch, microblaze]: Adjustments to pcmp instruction generation

[David Holsgrove]

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Adjustments to pcmp instruction generation

avoid pcmpe insns when not valuable

For pure in and equality comparisions, xor is better,
Xor is a one cycle insn as pcmp.

Pattern insns will still be used when you need to
conditionally set something to one or zero, e.g

if (a)
  return 1;
else
  return 0;

Define contraint for first operand in insn matching
fcmp as general register

Add a constraint to the cstoresf pattern forcing the use of
general regs for the operands. This avoids an ICE where the
compiler would crash on late usage of pseudo registers.

Changelog

2013-02-11  Edgar E. Iglesias <edgar.iglesias@gmail.com>

  * config/microblaze/microblaze.c (microblaze_emit_compare):
     Use xor for EQ/NE comparisions
  * config/microblaze/microblaze.md (cstoresf4): Add constraints
     (cbranchsf4): Adjust operator to comparison_operator


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From 28b71646b5a7ed7bc5471166f3661418f6dab24a Mon Sep 17 00:00:00 2001
From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Date: Sat, 19 Nov 2011 05:37:28 +0100
Subject: [PATCH] microblaze: Adjustments to pcmp instruction generation

avoid pcmpe insns when not valuable

For pure in and equality comparisions, xor is better,
Xor is a one cycle insn as pcmp.

Pattern insns will still be used when you need to
conditionally set something to one or zero, e.g

if (a)
  return 1;
else
  return 0;

Define contraint for first operand in insn matching
fcmp as general register

Add a constrain to the cstoresf pattern forcing the use of
general regs for the operands. This avoids an ICE where the
compiler would crash on late usage of pseudo registers.

Changelog

2013-02-11  Edgar E. Iglesias <edgar.iglesias@gmail.com>

  *  gcc/config/microblaze/microblaze.c (microblaze_emit_compare):
     Use xor for EQ/NE comparisions
  *  gcc/config/microblaze/microblaze.md (cstoresf4): Add constraints
     (cbranchsf4): Adjust operator to comparison_operator

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
---
 gcc/config/microblaze/microblaze.c  |   17 ++---------------
 gcc/config/microblaze/microblaze.md |   10 +++++-----
 2 files changed, 7 insertions(+), 20 deletions(-)

diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index 0fa4013..1567203 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -2917,21 +2917,8 @@ microblaze_emit_compare (enum machine_mode mode, rtx cmp, enum rtx_code *cmp_cod
 
   if (code == EQ || code == NE)
     {
-      if (TARGET_PATTERN_COMPARE && GET_CODE(cmp_op1) == REG) 
-        {
-          if (code == EQ) 
-	    {
-	      emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, cmp_op1));
-	      *cmp_code = NE;
-	    }
-	  else
-	    {    
-	      emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, cmp_op1));
-	    }
-        }
-      else
-	/* Use xor for equal/not-equal comparison.  */
-	emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
+      /* Use xor for equal/not-equal comparison.  */
+      emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
     }
   else if (code == GT || code == GTU || code == LE || code == LEU)
     {
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 6933546..49e7fb1 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -1651,10 +1651,10 @@
 ;; Setting a register from an floating point comparison. 
 ;;----------------------------------------------------------------
 (define_insn "cstoresf4"
-   [(set (match_operand:SI 0 "register_operand")
-        (match_operator:SI 1 "ordered_comparison_operator"
-	      [(match_operand:SF 2 "register_operand")
-	       (match_operand:SF 3 "register_operand")]))]
+   [(set (match_operand:SI 0 "register_operand" "=r")
+        (match_operator 1 "comparison_operator"
+	      [(match_operand:SF 2 "register_operand" "r")
+	       (match_operand:SF 3 "register_operand" "r")]))]
   "TARGET_HARD_FLOAT"
   "fcmp.%C1\t%0,%3,%2"
   [(set_attr "type"     "fcmp")
@@ -1681,7 +1681,7 @@
 
 (define_expand "cbranchsf4"
   [(set (pc)
-	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
+	(if_then_else (match_operator 0 "comparison_operator"
 		       [(match_operand:SF 1 "register_operand")
 		        (match_operand:SF 2 "register_operand")])
 		      (label_ref (match_operand 3 ""))
-- 
1.7.3.2

Re: [Patch, microblaze]: Adjustments to pcmp instruction generation

[Michael Eager]

On 02/10/2013 10:40 PM, David Holsgrove wrote:
> Adjustments to pcmp instruction generation
>
> avoid pcmpe insns when not valuable
>
> For pure in and equality comparisions, xor is better,
> Xor is a one cycle insn as pcmp.
>
> Pattern insns will still be used when you need to
> conditionally set something to one or zero, e.g
>
> if (a)
>    return 1;
> else
>    return 0;
>
> Define contraint for first operand in insn matching
> fcmp as general register
>
> Add a constraint to the cstoresf pattern forcing the use of
> general regs for the operands. This avoids an ICE where the
> compiler would crash on late usage of pseudo registers.
>
> Changelog
>
> 2013-02-11  Edgar E. Iglesias <edgar.iglesias@gmail.com>
>
>    * config/microblaze/microblaze.c (microblaze_emit_compare):
>       Use xor for EQ/NE comparisions
>    * config/microblaze/microblaze.md (cstoresf4): Add constraints
>       (cbranchsf4): Adjust operator to comparison_operator

Committed revision 196315.


-- 
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