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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id i15-20020a170902c94f00b001782aab6318sm10910298pla.68.2022.11.15.19.43.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Nov 2022 19:43:21 -0800 (PST) Message-ID: <9f2ad85c-e362-7f3d-5213-c61e61d64866@gmail.com> Date: Tue, 15 Nov 2022 20:43:19 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH] RISC-V: Use bseti to cover more immediates than with ori alone Content-Language: en-US To: Philipp Tomsich , gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Jeff Law , Christoph Muellner , Palmer Dabbelt , Kito Cheng References: <20221110213445.3592438-1-philipp.tomsich@vrull.eu> From: Jeff Law In-Reply-To: <20221110213445.3592438-1-philipp.tomsich@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 11/10/22 14:34, Philipp Tomsich wrote: > Sequences of the form "a | C" with C being the positive half of a > signed immediate's range with one extra bit set in addtion are mapped > to ori and one binvi to avoid using a temporary (and a multi-insn > sequence to load C into that temporary). > > gcc/ChangeLog: > > * config/riscv/bitmanip.md (*bseti_extrabit): New pattern > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zbs-bseti.c: New test. > > Signed-off-by: Philipp Tomsich > --- > - Depends on a predicate posted in "RISC-V: Optimize branches testing > a bit-range or a shifted immediate". Depending on the order of > applying these, I'll take care to pull that part out of the other > patch if needed. > > gcc/config/riscv/bitmanip.md | 19 +++++++++++++++ > gcc/testsuite/gcc.target/riscv/zbs-bseti.c | 27 ++++++++++++++++++++++ > 2 files changed, 46 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bseti.c > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > index 06126ac4819..436ff4ba958 100644 > --- a/gcc/config/riscv/bitmanip.md > +++ b/gcc/config/riscv/bitmani > @@ -512,6 +512,25 @@ > "bseti\t%0,%1,%S2" > [(set_attr "type" "bitmanip")]) > > +; Catch those cases where we can use a bseti + ori or bseti + bseti > +; instead of a lui + addi + or sequence. > +(define_insn_and_split "*bseti_extrabit" > + [(set (match_operand:X 0 "register_operand" "=r") > + (ior:X (match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "uimm_extra_bit_operand" "i")))] > + "TARGET_ZBS" > + "#" > + "&& reload_completed" > + [(set (match_dup 0) (ior:X (match_dup 1) (match_dup 3))) > + (set (match_dup 0) (ior:X (match_dup 0) (match_dup 4)))] > +{ > + unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]); > + unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits); > + > + operands[3] = GEN_INT (bits &~ topbit); > + operands[4] = GEN_INT (topbit); > +}) I briefly thought you might need an earlyclobber for the output, but you consume the input register in the first generated insn, so you should be OK. OK. jeff