[PATCH 0/3][ARC] Bug fixes, cleanups and doc update.

[PATCH 0/3][ARC] Bug fixes, cleanups and doc update.

[Claudiu Zissulescu]

Hi Andrew,

Please find a set of three patches for trunk as fallows:

  [ARC] Cleanup sign/zero extend patterns
  	This is just insn patterns cleanup.
  [ARC] Update mea option documentation
  	Update -mea option documentation.
  [ARC] Don't split ior/mov predicated insns.
  	Found a bug in the current trunk, this patch fixes it and adds a test.

 gcc/config/arc/arc.c                         |  16 ++-
 gcc/config/arc/arc.md                        | 118 +++++++++++--------
 gcc/config/arc/arc.opt                       |   2 +-
 gcc/doc/invoke.texi                          |   2 +-
 gcc/testsuite/gcc.target/arc/or-cnst-size2.c |  12 ++
 5 files changed, 91 insertions(+), 59 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arc/or-cnst-size2.c

-- 
2.21.0

[PATCH 2/3] [ARC] Update mea option documentation

[Claudiu Zissulescu]

Update -mea option documentation.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.opt (mea): Update help string.
	* doc/invoke.texi(ARC): Update mea option info.
---
 gcc/config/arc/arc.opt | 2 +-
 gcc/doc/invoke.texi    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index e2f1fc6a4cf..b76ca0fedc3 100644
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -167,7 +167,7 @@ Do not generate mpy instructions for ARC700.
 
 mea
 Target Report Mask(EA_SET)
-Generate Extended arithmetic instructions.  Currently only divaw, adds, subs and sat16 are supported.
+Generate extended arithmetic instructions, only valid for ARC700.
 
 msoft-float
 Target Report Mask(0)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1e10395b61e..aaa6039beaf 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16504,7 +16504,7 @@ aux registers.
 @opindex mea
 Generate extended arithmetic instructions.  Currently only
 @code{divaw}, @code{adds}, @code{subs}, and @code{sat16} are
-supported.  This is always enabled for @option{-mcpu=ARC700}.
+supported.  Only valid for @option{-mcpu=ARC700}.
 
 @item -mno-mpy
 @opindex mno-mpy
-- 
2.21.0

Re: [PATCH 2/3] [ARC] Update mea option documentation

[Jeff Law]

On 10/22/19 2:21 AM, Claudiu Zissulescu wrote:
> Update -mea option documentation.
> 
> gcc/
> xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.opt (mea): Update help string.
> 	* doc/invoke.texi(ARC): Update mea option info.
OK
jeff

[PATCH 1/3] [ARC] Cleanup sign/zero extend patterns

[Claudiu Zissulescu]

Cleanup sign/zero extend patterns (corrects the asm output string and constraint letters).

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (zero_extendqihi2_i): Cleanup pattern.
	(zero_extendqisi2_ac): Likewise.
	(zero_extendhisi2_i): Likewise.
	(extendqihi2_i): Likewise.
	(extendqisi2_ac): Likewise.
	(extendhisi2_i): Likewise.
---
 gcc/config/arc/arc.md | 105 ++++++++++++++++++++++--------------------
 1 file changed, 56 insertions(+), 49 deletions(-)

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index e1ecf7d3c73..e08aaf8f09a 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1838,18 +1838,22 @@ archs4x, archs4xd"
   [(set_attr "type" "cmove,cmove")
    (set_attr "length" "8,16")])
 
+;; -------------------------------------------------------------------
+;; Sign/Zero extension
+;; -------------------------------------------------------------------
 
 (define_insn "*zero_extendqihi2_i"
-  [(set (match_operand:HI 0 "dest_reg_operand" "=Rcq,Rcq#q,Rcw,w,r,r")
-	(zero_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "0,Rcq#q,0,c,Ucm,m")))]
+  [(set (match_operand:HI 0 "dest_reg_operand" "=q,q,r,r,r,r")
+	(zero_extend:HI
+	 (match_operand:QI 1 "nonvol_nonimm_operand" "0,q,0,r,Ucm,m")))]
   ""
   "@
-   extb%? %0,%1%&
-   extb%? %0,%1%&
-   bmsk%? %0,%1,7
-   extb %0,%1
-   xldb%U1 %0,%1
-   ldb%U1 %0,%1"
+   extb%?\\t%0,%1
+   extb%?\\t%0,%1
+   bmsk%?\\t%0,%1,7
+   extb\\t%0,%1
+   xldb%U1\\t%0,%1
+   ldb%U1\\t%0,%1"
   [(set_attr "type" "unary,unary,unary,unary,load,load")
    (set_attr "iscompact" "maybe,true,false,false,false,false")
    (set_attr "predicable" "no,no,yes,no,no,no")])
@@ -1862,18 +1866,19 @@ archs4x, archs4xd"
 )
 
 (define_insn "*zero_extendqisi2_ac"
-  [(set (match_operand:SI 0 "dest_reg_operand"    "=Rcq,Rcq#q,Rcw,w,qRcq,!*x,r,r")
-	(zero_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "0,Rcq#q,0,c,T,Usd,Ucm,m")))]
+  [(set (match_operand:SI 0 "dest_reg_operand"    "=q,q,r,r,q,!*x,r,r")
+	(zero_extend:SI
+	 (match_operand:QI 1 "nonvol_nonimm_operand" "0,q,0,r,T,Usd,Ucm,m")))]
   ""
   "@
-   extb%? %0,%1%&
-   extb%? %0,%1%&
-   bmsk%? %0,%1,7
-   extb %0,%1
-   ldb%? %0,%1%&
-   ldb%? %0,%1%&
-   xldb%U1 %0,%1
-   ldb%U1 %0,%1"
+   extb%?\\t%0,%1
+   extb%?\\t%0,%1
+   bmsk%?\\t%0,%1,7
+   extb\\t%0,%1
+   ldb%?\\t%0,%1
+   ldb%?\\t%0,%1
+   xldb%U1\\t%0,%1
+   ldb%U1\\t%0,%1"
   [(set_attr "type" "unary,unary,unary,unary,load,load,load,load")
    (set_attr "iscompact" "maybe,true,false,false,true,true,false,false")
    (set_attr "predicable" "no,no,yes,no,no,no,no,no")])
@@ -1886,23 +1891,23 @@ archs4x, archs4xd"
 )
 
 (define_insn "*zero_extendhisi2_i"
-  [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,q,Rcw,w,!x,Rcqq,r,r")
-	(zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "0,q,0,c,Usd,T,Ucm,m")))]
+  [(set (match_operand:SI 0 "dest_reg_operand" "=q,q,r,r,!x,q,r,r")
+	(zero_extend:SI
+	 (match_operand:HI 1 "nonvol_nonimm_operand" "0,q,0,r,Usd,T,Ucm,m")))]
   ""
   "@
-   ext%_%? %0,%1%&
-   ext%_%? %0,%1%&
-   bmsk%? %0,%1,15
-   ext%_ %0,%1
-   ld%_%? %0,%1
-   ld%_%? %0,%1
-   * return TARGET_EM ? \"xldh%U1%V1 %0,%1\" : \"xldw%U1 %0,%1\";
-   ld%_%U1%V1 %0,%1"
+   ext%_%?\\t%0,%1
+   ext%_%?\\t%0,%1
+   bmsk%?\\t%0,%1,15
+   ext%_\\t%0,%1
+   ld%_%?\\t%0,%1
+   ld%_%?\\t%0,%1
+   xldw%U1\\t%0,%1
+   ld%_%U1%V1\\t%0,%1"
   [(set_attr "type" "unary,unary,unary,unary,load,load,load,load")
    (set_attr "iscompact" "maybe,true,false,false,true,true,false,false")
    (set_attr "predicable" "no,no,yes,no,no,no,no,no")])
 
-
 (define_expand "zero_extendhisi2"
   [(set (match_operand:SI 0 "dest_reg_operand" "")
 	(zero_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "")))]
@@ -1913,19 +1918,19 @@ archs4x, archs4xd"
 ;; Sign extension instructions.
 
 (define_insn "*extendqihi2_i"
-  [(set (match_operand:HI 0 "dest_reg_operand" "=Rcqq,r,r,r")
-	(sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "Rcqq,r,Uex,m")))]
+  [(set (match_operand:HI 0 "dest_reg_operand" "=q,r,r,r")
+	(sign_extend:HI
+	 (match_operand:QI 1 "nonvol_nonimm_operand" "q,r,Uex,m")))]
   ""
   "@
-   sexb%? %0,%1%&
-   sexb %0,%1
-   ldb.x%U1 %0,%1
-   ldb.x%U1 %0,%1"
+   sexb%?\\t%0,%1
+   sexb\\t%0,%1
+   ldb.x%U1\\t%0,%1
+   ldb.x%U1\\t%0,%1"
   [(set_attr "type" "unary,unary,load,load")
    (set_attr "iscompact" "true,false,false,false")
    (set_attr "length" "*,*,*,8")])
 
-
 (define_expand "extendqihi2"
   [(set (match_operand:HI 0 "dest_reg_operand" "")
 	(sign_extend:HI (match_operand:QI 1 "nonvol_nonimm_operand" "")))]
@@ -1934,14 +1939,15 @@ archs4x, archs4xd"
 )
 
 (define_insn "*extendqisi2_ac"
-  [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,r,r")
-	(sign_extend:SI (match_operand:QI 1 "nonvol_nonimm_operand" "Rcqq,c,Uex,m")))]
+  [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,r,r")
+	(sign_extend:SI
+	 (match_operand:QI 1 "nonvol_nonimm_operand" "q,r,Uex,m")))]
   ""
   "@
-   sexb%? %0,%1%&
-   sexb %0,%1
-   ldb.x%U1 %0,%1
-   ldb.x%U1 %0,%1"
+   sexb%?\\t%0,%1
+   sexb\\t%0,%1
+   ldb.x%U1\\t%0,%1
+   ldb.x%U1\\t%0,%1"
   [(set_attr "type" "unary,unary,load,load")
    (set_attr "iscompact" "true,false,false,false")
    (set_attr "length" "*,*,*,8")])
@@ -1954,15 +1960,16 @@ archs4x, archs4xd"
 )
 
 (define_insn "*extendhisi2_i"
-  [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w,Rcqq,r,r")
-	(sign_extend:SI (match_operand:HI 1 "nonvol_nonimm_operand" "Rcqq,c,Ucd,Uex,m")))]
+  [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,q,r,r")
+	(sign_extend:SI
+	 (match_operand:HI 1 "nonvol_nonimm_operand" "q,r,Ucd,Uex,m")))]
   ""
   "@
-   sex%_%? %0,%1%&
-   sex%_ %0,%1
-   ldh%?.x %0,%1%&
-   ld%_.x%U1%V1 %0,%1
-   ld%_.x%U1%V1 %0,%1"
+   sex%_%?\\t%0,%1
+   sex%_\\t%0,%1
+   ldh%?.x\\t%0,%1%&
+   ld%_.x%U1%V1\\t%0,%1
+   ld%_.x%U1%V1\\t%0,%1"
   [(set_attr "type" "unary,unary,load,load,load")
    (set_attr "iscompact" "true,false,true,false,false")
    (set_attr "length" "*,*,*,4,8")])
-- 
2.21.0

Re: [PATCH 1/3] [ARC] Cleanup sign/zero extend patterns

[Jeff Law]

On 10/22/19 2:21 AM, Claudiu Zissulescu wrote:
> Cleanup sign/zero extend patterns (corrects the asm output string and constraint letters).
> 
> gcc/
> xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.md (zero_extendqihi2_i): Cleanup pattern.
> 	(zero_extendqisi2_ac): Likewise.
> 	(zero_extendhisi2_i): Likewise.
> 	(extendqihi2_i): Likewise.
> 	(extendqisi2_ac): Likewise.
> 	(extendhisi2_i): Likewise.
OK.

Jeff

[PATCH 3/3] [ARC] Don't split ior/mov predicated insns.

[Claudiu Zissulescu]

Do not split immediate constants for predicated instructions.

gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_split_ior): Add asserts.
	(arc_split_mov_const): Likewise.
	(arc_check_ior_const): Do not match known short immediate values.
	* config/arc/arc.md (movsi): Don't split predicated instructions.
	(iorsi): Likewise.

testsuite/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
	Sahahb Vahedi  <shahab@synopsys.com>
	Cupertino Miranda  <cmiranda@synopsys.com>

	* gcc.target/arc/or-cnst-size2.c: New test.
---
 gcc/config/arc/arc.c                         | 16 +++++++++++-----
 gcc/config/arc/arc.md                        | 13 ++++++++++---
 gcc/testsuite/gcc.target/arc/or-cnst-size2.c | 12 ++++++++++++
 3 files changed, 33 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arc/or-cnst-size2.c

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 9c4dee50494..fe5ee8f4104 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -11540,8 +11540,10 @@ arc_split_ior (rtx *operands)
       emit_insn (gen_rtx_SET (operands[0],
 			      gen_rtx_IOR (SImode, op1, GEN_INT (maskx))));
       break;
-    default:
+    case 0:
       break;
+    default:
+      gcc_unreachable ();
     }
 }
 
@@ -11551,6 +11553,10 @@ bool
 arc_check_ior_const (HOST_WIDE_INT ival)
 {
   unsigned int mask = (unsigned int) (ival & 0xffffffff);
+
+  if (UNSIGNED_INT6 (ival)
+      || IS_POWEROF2_P (mask))
+    return false;
   if (__builtin_popcount (mask) <= 3)
     return true;
   if (__builtin_popcount (mask & ~0x3f) <= 1)
@@ -11572,9 +11578,6 @@ arc_split_mov_const (rtx *operands)
   gcc_assert (CONST_INT_P (operands[1]));
   ival = INTVAL (operands[1]) & 0xffffffff;
 
-  if (SIGNED_INT12 (ival))
-    return false;
-
   /* 1. Check if we can just rotate limm by 8 but using ROR8.  */
   if (TARGET_BARREL_SHIFTER && TARGET_V2
       && ((ival & ~0x3f000000) == 0))
@@ -11641,7 +11644,7 @@ arc_split_mov_const (rtx *operands)
       return true;
     }
 
-  return false;
+  gcc_unreachable ();
 }
 
 /* Helper to check Cax constraint.  */
@@ -11651,6 +11654,9 @@ arc_check_mov_const (HOST_WIDE_INT ival)
 {
   ival = ival & 0xffffffff;
 
+  if (SIGNED_INT12 (ival))
+    return false;
+
   if ((ival & ~0x8000001f) == 0)
     return true;
 
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index e08aaf8f09a..d2b7a45b6e6 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -825,8 +825,11 @@ archs4x, archs4xd"
    st%U0%V0\\t%1,%0	;26
    st%U0%V0\\t%1,%0	;37
    st%U0%V0\\t%1,%0	;28"
-  "reload_completed && satisfies_constraint_Cax (operands[1])
-   && register_operand (operands[0], SImode)"
+  "reload_completed
+   && GET_CODE (PATTERN (insn)) != COND_EXEC
+   && register_operand (operands[0], SImode)
+   && IN_RANGE (REGNO (operands[0]) ^ 4, 4, 11)
+   && satisfies_constraint_Cax (operands[1])"
   [(const_int 0)]
   "
    arc_split_mov_const (operands);
@@ -3399,7 +3402,11 @@ archs4x, archs4xd"
    #
    or%?\\t%0,%1,%2
    or%?\\t%0,%1,%2"
-  "reload_completed && satisfies_constraint_C0x (operands[2])"
+  "reload_completed
+   && GET_CODE (PATTERN (insn)) != COND_EXEC
+   && register_operand (operands[0], SImode)
+   && IN_RANGE (REGNO (operands[0]) ^ 4, 4, 11)
+   && satisfies_constraint_C0x (operands[2])"
   [(const_int 0)]
   "
    arc_split_ior (operands);
diff --git a/gcc/testsuite/gcc.target/arc/or-cnst-size2.c b/gcc/testsuite/gcc.target/arc/or-cnst-size2.c
new file mode 100644
index 00000000000..33af97bbdbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/or-cnst-size2.c
@@ -0,0 +1,12 @@
+/* Check if we optimize the immediate of a predicated instruction.  */
+/* { dg-options "-Os -fif-conversion -fif-conversion2" } */
+
+int a;
+int foo (void)
+{
+  if ((a & 60) == 0)
+    return a | 64;
+}
+
+/* { dg-final { scan-assembler "tst" } } */
+/* { dg-final { scan-assembler "bset.eq" } } */
-- 
2.21.0

Re: [PATCH 3/3] [ARC] Don't split ior/mov predicated insns.

[Jeff Law]

On 10/22/19 2:21 AM, Claudiu Zissulescu wrote:
> Do not split immediate constants for predicated instructions.
> 
> gcc/
> xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.c (arc_split_ior): Add asserts.
> 	(arc_split_mov_const): Likewise.
> 	(arc_check_ior_const): Do not match known short immediate values.
> 	* config/arc/arc.md (movsi): Don't split predicated instructions.
> 	(iorsi): Likewise.
> 
> testsuite/
> xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
> 	Sahahb Vahedi  <shahab@synopsys.com>
> 	Cupertino Miranda  <cmiranda@synopsys.com>
> 
> 	* gcc.target/arc/or-cnst-size2.c: New test.
OK
jeff