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Tue, 21 May 2024 04:57:39 +0000 (GMT) Message-ID: <9fbecbc5-bdf7-45a8-8cec-7987cbfcbf23@linux.ibm.com> Date: Tue, 21 May 2024 10:27:37 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PING^4][PATCH] rs6000: load high and low part of 128bit vector independently [PR110040] From: jeevitha To: jeevitha , GCC Patches , "Kewen.Lin" , Segher Boessenkool , Michael Meissner Cc: Peter Bergner References: <1a62a215-98e2-4e3b-9059-681189157d0a@linux.vnet.ibm.com> <15fad1e9-ce60-4788-8192-514f91b62edd@linux.ibm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: t2TonEWpfZgrIkXcvVyE5cexCLvuN8ok X-Proofpoint-GUID: t2TonEWpfZgrIkXcvVyE5cexCLvuN8ok X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-21_02,2024-05-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405210037 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Ping! please review. Thanks & Regards Jeevitha On 17/04/24 2:46 pm, jeevitha wrote: > Ping! > > please review. > > Thanks & Regards > Jeevitha > > On 26/03/24 10:23 am, jeevitha wrote: >> Ping! >> >> please review. >> >> Thanks & Regards >> Jeevitha >> >> >> On 26/02/24 11:13 am, jeevitha wrote: >>> Hi All, >>> >>> The following patch has been bootstrapped and regtested on powerpc64le-linux. >>> >>> PR110040 exposes an issue concerning moves from vector registers to GPRs. >>> There are two moves, one for upper 64 bits and the other for the lower >>> 64 bits. In the problematic test case, we are only interested in storing >>> the lower 64 bits. However, the instruction for copying the upper 64 bits >>> is still emitted and is dead code. This patch adds a splitter that splits >>> apart the two move instructions so that DCE can remove the dead code after >>> splitting. >>> >>> 2024-02-26 Jeevitha Palanisamy >>> >>> gcc/ >>> PR target/110040 >>> * config/rs6000/vsx.md (split pattern for V1TI to DI move): Defined. >>> >>> gcc/testsuite/ >>> PR target/110040 >>> * gcc.target/powerpc/pr110040-1.c: New testcase. >>> * gcc.target/powerpc/pr110040-2.c: New testcase. >>> >>> >>> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md >>> index 6111cc90eb7..78457f8fb14 100644 >>> --- a/gcc/config/rs6000/vsx.md >>> +++ b/gcc/config/rs6000/vsx.md >>> @@ -6706,3 +6706,19 @@ >>> "vmsumcud %0,%1,%2,%3" >>> [(set_attr "type" "veccomplex")] >>> ) >>> + >>> +(define_split >>> + [(set (match_operand:V1TI 0 "int_reg_operand") >>> + (match_operand:V1TI 1 "vsx_register_operand"))] >>> + "reload_completed >>> + && TARGET_DIRECT_MOVE_64BIT" >>> + [(pc)] >>> +{ >>> + rtx op0 = gen_rtx_REG (DImode, REGNO (operands[0])); >>> + rtx op1 = gen_rtx_REG (V2DImode, REGNO (operands[1])); >>> + rtx op2 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1); >>> + rtx op3 = gen_rtx_REG (V2DImode, REGNO (operands[1])); >>> + emit_insn (gen_vsx_extract_v2di (op0, op1, GEN_INT (0))); >>> + emit_insn (gen_vsx_extract_v2di (op2, op3, GEN_INT (1))); >>> + DONE; >>> +}) >>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c >>> new file mode 100644 >>> index 00000000000..fb3bd254636 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c >>> @@ -0,0 +1,14 @@ >>> +/* PR target/110040 */ >>> +/* { dg-do compile } */ >>> +/* { dg-require-effective-target powerpc_p9vector_ok } */ >>> +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ >>> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ >>> + >>> +#include >>> + >>> +void >>> +foo (signed long *dst, vector signed __int128 src) >>> +{ >>> + *dst = (signed long) src[0]; >>> +} >>> + >>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c >>> new file mode 100644 >>> index 00000000000..f3aa22be4e8 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c >>> @@ -0,0 +1,13 @@ >>> +/* PR target/110040 */ >>> +/* { dg-do compile } */ >>> +/* { dg-require-effective-target power10_ok } */ >>> +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ >>> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ >>> + >>> +#include >>> + >>> +void >>> +foo (signed int *dst, vector signed __int128 src) >>> +{ >>> + __builtin_vec_xst_trunc (src, 0, dst); >>> +} >>> >>>