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From: <juzhe.zhong@rivai.ai>
To: gcc-patches <gcc-patches@gcc.gnu.org>
Cc: "Jeff Law" <jeffreyalaw@gmail.com>,
	 kito.cheng <kito.cheng@sifive.com>,  palmer <palmer@dabbelt.com>,
	 "Michael Collison" <collison@rivosinc.com>
Subject: RISC-V: Add auto-vectorization support
Date: Sat, 4 Mar 2023 08:29:10 +0800	[thread overview]
Message-ID: <A15233AED926A613+2023030408290974932731@rivai.ai> (raw)

[-- Attachment #1: Type: text/plain, Size: 2192 bytes --]

>> This series of patches adds foundational support for RISC-V 
>> autovectorization. These patches are based on the current upstream rvv 
>> vector intrinsic support and is not a new implementation. Most of the 
>> implementation consists of adding the new vector cost model, the 
>> autovectorization patterns themselves and target hooks.
>> This implementation only provides support for integer addition and 
>> subtraction as a proof of concept.
>> As discussed on this list, if these patches are approved they will be 
>> merged into a "auto-vectorization" branch once gcc-13 branches for release.
>> There are two known issues related to crashes (assert failures) 
>> associated with tree vectorization; one of which I have sent a patch for 
>> and have received feedback. I will be sending a patch for the second 
>> issue tomorrow.

These patches have so many issues:
1. You should not arithmetic operation without supporting auto-vectorization load/stores.
2. RVV cost model is totally incorrect since they are just my experimental work without any
    benchmark tuning.
3. ICE in auto-vectorization base on current upstream framework.
4. The vector-length/LMUL compile option is not ratified, we can't push the unratified
    compile option. The compile option should be consistent with LLVM.
5. The current RVV instruction machine descriptions are not stable, you can not support auto-vec
    base on unstable machine descriptions.
....etc. so many issues.

So I totally disagree this set of pathes. These patches are coming from my original ugly experimental 
RVV work in RISC-V repo:
https://github.com/riscv-collab/riscv-gcc/tree/riscv-gcc-rvv-next  that I already abandoned (I no longer maintained). 

Currently, we (I && kito) have finished all intrinsics (except segment instructions) and machine descriptions,
we will keep testing and fine-tunning && fix bugs until GCC 13 release.  We should wait until machine descriptions
are stable to support auto-vec. So don't do any auto-vec during stage 4 in GCC 13 plz. 

I have an elegent implementation in my downstream.
And I will start to auto-vec when GCC 14 is open.

Thanks.


juzhe.zhong@rivai.ai

                 reply	other threads:[~2023-03-04  0:29 UTC|newest]

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