[PATCH V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions

[PATCH V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions

[Lehua Ding]

V2 Change: Use Robin's comments.

This patch adjusts the comments of the
emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions.
The purpose of the adjustment is to make it clear that vlmax here is not
VLMAX as defined inside the RVV ISA. This is because this function is used
by RVV mode (e.g. RVVM1SImode) in addition to VLS mode (V16QI). For RVV mode,
it means the same thing, for VLS mode, it indicates setting the vl to the
number of units of the mode. Changed the comment because I didn't think of
a better name. If there is a suitable name, feel free to discuss it.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (emit_vlmax_insn): Adjust comments.
	(emit_nonvlmax_insn): Adjust comments.
	(emit_vlmax_insn_lra): Adjust comments.

Co-Authored-By: Robin Dapp <rdapp.gcc@gmail.com>

---
 gcc/config/riscv/riscv-v.cc | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 64a71a128d4..bb08289d39a 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -347,33 +347,42 @@ private:
   expand_operand m_ops[MAX_OPERANDS];
 };

-/* Emit RVV insn which vl is VLMAX.
-   This function can only be used before LRA pass or
-   for VLS_AVL_IMM modes.  */
+/* Emit an RVV insn with a vector length that equals the number of units of the
+   vector mode.  For VLA modes this corresponds to VLMAX.
+
+   Unless the vector length can be encoded in the vsetivl[i] instruction this
+   function must only be used as long as we can create pseudo registers. This is
+   because it will set a pseudo register to VLMAX using vsetvl and use this as
+   definition for the vector length.  */
 void
 emit_vlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops)
 {
   insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
+  gcc_assert (can_create_pseudo_p () || const_vlmax_p (e.get_vtype_mode (ops)));
+
   e.emit_insn ((enum insn_code) icode, ops);
 }

-/* Emit RVV insn which vl is VL.  */
+/* Like emit_vlmax_insn but must only be used when we cannot create pseudo
+   registers anymore.  This function, however, takes a predefined vector length
+   from the value in VL. */
 void
-emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
+emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
 {
-  insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, false);
+  gcc_assert (!can_create_pseudo_p ());
+
+  insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
   e.set_vl (vl);
   e.emit_insn ((enum insn_code) icode, ops);
 }

-/* Emit RVV insn which vl is VL but the AVL_TYPE insn attr is VLMAX.
-   This function used after LRA pass that cann't create pseudo register.  */
+/* Emit an RVV insn with a predefined vector length.  Contrary to
+   emit_vlmax_insn the instruction's vector length is not deduced from its mode
+   but taken from  the value in VL.  */
 void
-emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
+emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
 {
-  gcc_assert (!can_create_pseudo_p ());
-
-  insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
+  insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, false);
   e.set_vl (vl);
   e.emit_insn ((enum insn_code) icode, ops);
 }
--
2.36.3

Re: [PATCH V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions

[Robin Dapp]

LGTM.

Regards
 Robin

Re: [PATCH V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions

[Lehua Ding]

Committed, thanks Robin.

On 2023/9/21 17:57, Robin Dapp wrote:
> LGTM.
> 
> Regards
>   Robin

-- 
Best,
Lehua (RiVAI)
lehua.ding@rivai.ai