From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by sourceware.org (Postfix) with ESMTPS id 65E323858D1E; Fri, 23 Dec 2022 16:20:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 65E323858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=suse.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=suse.de Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id E2DAA267CF; Fri, 23 Dec 2022 16:20:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1671812419; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6qrupvnpXB61JlsnxKtlWtRbHFip8xdZTK000trWKX0=; b=RPiS1PPhgj/VaxVL7jV51FjlPdKZNyhXp+oj23PVFXe1azTlpFpjLnxEYdMnQQnjPOcQJQ zIJ6M/vJ8hgWWPHHGSTFQsyeMQfj0ccRN8i74nkSwy0SVqwa8fcoDB8IjUuUHBuVpuhHZN mspxeueexhWJKFjQaqGYoszzLfivhPc= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671812419; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6qrupvnpXB61JlsnxKtlWtRbHFip8xdZTK000trWKX0=; b=LCjvXqaC1hjGCrjL9d9esurkW//5WuzXVPabY8OmW+Wi/oRIvI2Sie00oZftql48hbTMR1 1iCk9WxVKjL5ZIBg== Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id D17AC13913; Fri, 23 Dec 2022 16:20:19 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id ZOAZM0PVpWP0FQAAMHmgww (envelope-from ); Fri, 23 Dec 2022 16:20:19 +0000 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Richard Biener Mime-Version: 1.0 (1.0) Subject: Re: [PATCH] loading float member of parameter stored via int registers Date: Fri, 23 Dec 2022 17:20:09 +0100 Message-Id: References: <20221223144509.GZ25951@gate.crashing.org> Cc: Jiufu Guo , Jiufu Guo via Gcc-patches , dje.gcc@gmail.com, linkw@gcc.gnu.org, jeffreyalaw@gmail.com In-Reply-To: <20221223144509.GZ25951@gate.crashing.org> To: Segher Boessenkool X-Mailer: iPhone Mail (20C65) X-Spam-Status: No, score=-5.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > Am 23.12.2022 um 15:48 schrieb Segher Boessenkool : >=20 > =EF=BB=BFHi! >=20 >> On Fri, Dec 23, 2022 at 08:36:36PM +0800, Jiufu Guo wrote: >> It seems some limitations there. e.g. 1. "subreg:DF on DI register" >> may not work well on pseudo, >=20 > It is perfectly normal: > A hard register may be accessed in various modes throughout one > function, but each pseudo register is given a natural mode > and is accessed only in that mode. When it is necessary to describe > an access to a pseudo register using a nonnatural mode, a @code{subreg} > expression is used. >=20 > and: > @code{subreg} expressions are used to refer to a register in a machine > mode other than its natural one, or to refer to one register of > a multi-part @code{reg} that actually refers to several registers. >=20 > Each pseudo register has a natural mode. If it is necessary to > operate on it in a different mode, the register must be > enclosed in a @code{subreg}. >=20 > and we even have: > @item hard registers > It is seldom necessary to wrap hard registers in @code{subreg}s; such > registers would normally reduce to a single @code{reg} rtx. This use of > @code{subreg}s is discouraged and may not be supported in the future. >=20 >> and 2. to convert high-part:DI to SF, >> a "shift/rotate" is needed, and then we need to "emit shift insn" >> in cse. I may need to update this patch. >=20 > Hrm. The machine insns to do this is just mtvsrd;xscvspdpn, but for > converting the lowpart it is mtvsrws;xscvspdpn (this needs p9 or > later). We should arrive at those patterns, and we should try to not > go via the more expensive formulations with shifts, which don't describe > the hardware well, and which overestimate the cost of it. >=20 > None of this belongs in generic code at all imo. At expand time it > should be expanded to something that works and can be optimised well, > so not anything with :BLK (which has to be put in memory, something with > unbounded size cannot be put in registers), not anything specifically > tailored to any cpu, something nice and regular. Using a subreg (of a > pseudo!) is the standard way of writing a bitcast. >=20 > So generic code would do a (subreg:SF (reg:SI) 0) to express a 32-bit > integer bitcast to an IEEE SP number, and our machine description should > make it work nicely. There=E2=80=99s also a byte offset in subreg, so (subreg:sf (reg:di) 4) is a= Highpart bitcast. Note whether targets actually support subreg operations n= eeds to be queried and I=E2=80=99m not sure how subreg with offset validatio= n should work there. Richard=20 >=20 >=20 > Segher