Re: Re: [PATCH] RISC-V: Fix RVV testcases.

[钟居哲 <juzhe.zhong@rivai.ai>]

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These cases actually doesn't care about -mabi, they just need 'v' in -march.
Can you tell me how to fix these testcases for "fails on targets without ilp32d" ?
These failures are bogus failures since if you specify -mabi=ilp32d when you are using GNU toolchain which is build up with "--arch=ilp32" let say.
It will fail. Report there is no "ilp32d". So I fix these testcase by replacing "ilp32d" into "ilp32".
Thank you.



juzhe.zhong@rivai.ai
 
From: Palmer Dabbelt
Date: 2022-11-01 06:30
To: gcc-patches
CC: juzhe.zhong; gcc-patches; schwab; Kito Cheng
Subject: Re: [PATCH] RISC-V: Fix RVV testcases.
On Mon, 31 Oct 2022 15:00:49 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
>
> On 10/30/22 19:40, juzhe.zhong@rivai.ai wrote:
>> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>>
>> gcc/testsuite/ChangeLog:
>>
>>          * gcc.target/riscv/rvv/base/abi-2.c: Change ilp32d to ilp32.
>>          * gcc.target/riscv/rvv/base/abi-3.c: Ditto.
>>          * gcc.target/riscv/rvv/base/abi-4.c: Ditto.
>>          * gcc.target/riscv/rvv/base/abi-5.c: Ditto.
>>          * gcc.target/riscv/rvv/base/abi-6.c: Ditto.
>>          * gcc.target/riscv/rvv/base/abi-7.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-1.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-10.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-11.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-12.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-13.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-2.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-3.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-4.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-5.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-6.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-7.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-8.c: Ditto.
>>          * gcc.target/riscv/rvv/base/mov-9.c: Ditto.
>>          * gcc.target/riscv/rvv/base/pragma-1.c: Ditto.
>>          * gcc.target/riscv/rvv/base/user-1.c: Ditto.
>>          * gcc.target/riscv/rvv/base/user-2.c: Ditto.
>>          * gcc.target/riscv/rvv/base/user-3.c: Ditto.
>>          * gcc.target/riscv/rvv/base/user-4.c: Ditto.
>>          * gcc.target/riscv/rvv/base/user-5.c: Ditto.
>>          * gcc.target/riscv/rvv/base/user-6.c: Ditto.
>>          * gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
>
> I'm pretty new to the RISC-V world, but don't some of the cases
> (particularly the abi-* tests) verify that the ABI specification does
> not override the arch specification WRT availability of types?
 
I think that depends on what the ABI specification says here, as it 
could really go many ways.  Most of the RISC-V targets just use -mabi to 
control how arguments end up passed in functions, not the availability 
of types.  I can't find the ABI spec for these, though, so I'm not 
entirely sure how they're supposed to work...
 
That said, I'm not sure why we need any of these -mabi changes?  Just 
from spot checking some of the examples it doesn't look like there 
should be any functional difference between ilp32 and ilp32d here: 
-march is always specified so ilp32d looks valid.  If this is just to 
fix the "fails on targets without ilp32d" [1], then IMO it's not really 
a fix: we're essentially just changing that to "fails on targets without 
ilp32", we either need some sort of automatic march/mabi setting or a 
dependency on the availiable multilibs.  Some of these can probably 
avoid linking, but we'll have execution tests at some point.
 
1: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604644.html