* [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
@ 2015-03-30 21:52 Evandro Menezes
2015-03-31 8:33 ` Kyrill Tkachov
0 siblings, 1 reply; 11+ messages in thread
From: Evandro Menezes @ 2015-03-30 21:52 UTC (permalink / raw)
To: 'GCC Patches'
[-- Attachment #1: Type: text/plain, Size: 275 bytes --]
The Samsung Exynos M1 implements the ARMv8 ISA and this patch adds support
for it through the -mcpu command-line option.
The patch was checked on arm-unknown-linux-gnueabihf without new failures.
OK for trunk?
--
Evandro Menezes Austin, TX
[-- Attachment #2: 0001-ARM-Add-option-for-the-Samsung-Exynos-M1-core-for-AR.patch --]
[-- Type: application/octet-stream, Size: 3756 bytes --]
From 5951140f9c1ba428533b9b4e2d98a8c2bd3517c1 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Fri, 20 Mar 2015 15:43:07 -0500
Subject: [PATCH] [ARM] Add option for the Samsung Exynos M1 core for ARM
gcc/
* doc/invoke.texi (ARM/mtune): Add exynos-m1 as an option.
* config/arm/arm-cores.def (exynos-m1): New core.
* config/arm/arm-tune.md: Regenerate.
* config/arm/arm-tables.opt: Add entry for "exynos-m1".
* config/arm/bpabi.h: Likewise.
---
gcc/config/arm/arm-cores.def | 1 +
gcc/config/arm/arm-tables.opt | 3 +++
gcc/config/arm/arm-tune.md | 2 +-
gcc/config/arm/bpabi.h | 2 ++
gcc/doc/invoke.texi | 1 +
5 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index b22ea7f..0710a38 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -168,6 +168,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, FL_LDSCHED |
ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a53)
ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
+ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, FL_LDSCHED | FL_CRC32, exynosm1)
ARM_CORE("xgene1", xgene1, xgene1, 8A, FL_LDSCHED, xgene1)
/* V8 big.LITTLE implementations */
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 3450e5b..510e745 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -313,6 +313,9 @@ EnumValue
Enum(processor_type) String(cortex-a72) Value(cortexa72)
EnumValue
+Enum(processor_type) String(exynos-m1) Value(exynosm1)
+
+EnumValue
Enum(processor_type) String(xgene1) Value(xgene1)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index d459f27..f054617 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -32,6 +32,6 @@
cortexr4f,cortexr5,cortexr7,
cortexm7,cortexm4,cortexm3,
marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
- cortexa53,cortexa57,cortexa72,
+ cortexa53,cortexa57,cortexa72,exynosm1,
xgene1,cortexa57cortexa53,cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index c62130d..ceaf2cc 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -73,6 +73,7 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
+ |mcpu=exynos-m1 \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
@@ -97,6 +98,7 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
+ |mcpu=exynos-m1 \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 19606e3..9eec108 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13192,6 +13192,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m1.small-multiply},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
+@samp{exynos-m1},
@samp{marvell-pj4},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},
--
2.1.0.243.g30d45f7
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-03-30 21:52 [PATCH] [ARM] Add support for the Samsung Exynos M1 processor Evandro Menezes
@ 2015-03-31 8:33 ` Kyrill Tkachov
2015-04-01 0:31 ` Evandro Menezes
0 siblings, 1 reply; 11+ messages in thread
From: Kyrill Tkachov @ 2015-03-31 8:33 UTC (permalink / raw)
To: Evandro Menezes, 'GCC Patches'
Hi Evandro
On 30/03/15 22:51, Evandro Menezes wrote:
> The Samsung Exynos M1 implements the ARMv8 ISA and this patch adds support
> for it through the -mcpu command-line option.
>
> The patch was checked on arm-unknown-linux-gnueabihf without new failures.
>
> OK for trunk?
>
> -- Evandro Menezes Austin, TX
>
> 0001-ARM-Add-option-for-the-Samsung-Exynos-M1-core-for-AR.patch
>
>
> diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
> index b22ea7f..0710a38 100644
> --- a/gcc/config/arm/arm-cores.def
> +++ b/gcc/config/arm/arm-cores.def
> @@ -168,6 +168,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, FL_LDSCHED |
> ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a53)
> ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
> ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
> +ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, FL_LDSCHED | FL_CRC32, exynosm1)
There are two problems with this:
* The 3rd field of ARM_CORE represents the scheduling identifier and
without a
separate pipeline description for exynosm1 this will just use the
generic_sched
scheduler which performs quite poorly on modern cores. Would you prefer to
reuse a pipeline description from one of the pre-existing ones? Look for
example
at the cortex-a72 definition:
ARM_CORE("cortex-a72", cortexa72, cortexa57, <...snip>
here the cortexa57 means 'make scheduling decisions for cortexa57'.
* The final field in ARM_CORE specifies the tuning struct to be used for
this core.
This should be defined in arm.c and have the form 'arm_<ident>_tune, so
for your
case it should be arm_exynosm1_tune. This isn't defined in your patch,
so it won't
compile without that. You can write a custom tuning struct yourself, or
reuse a
tuning struct for one of the existing cores, if you'd like.
Also, you should add exynosm1 to the switch statement in arm_issue_rate
to specify
the issue rate. I have a patch for next stage1 that should refactor it
all into the
tuning structs
(https://gcc.gnu.org/ml/gcc-patches/2014-11/msg02706.html) but until
that goes in, you should fill in the switch statement there.
Thanks,
Kyrill
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-03-31 8:33 ` Kyrill Tkachov
@ 2015-04-01 0:31 ` Evandro Menezes
2015-04-02 22:19 ` Sebastian Pop
0 siblings, 1 reply; 11+ messages in thread
From: Evandro Menezes @ 2015-04-01 0:31 UTC (permalink / raw)
To: 'Kyrill Tkachov', 'GCC Patches'
[-- Attachment #1: Type: text/plain, Size: 2915 bytes --]
Hi, Kyrill.
At this moment, it suffices to use the same scheduling as Cortex A57, but
more specific details are to be expected.
I couldn't check the build though, as my Arndale is strange today. As soon
as it's healthy, I'll check it.
I appreciate your feedback.
--
Evandro Menezes Austin, TX
> -----Original Message-----
> From: Kyrill Tkachov [mailto:kyrylo.tkachov@arm.com]
> Sent: Tuesday, March 31, 2015 3:33
> To: Evandro Menezes; 'GCC Patches'
> Subject: Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
>
> Hi Evandro
> On 30/03/15 22:51, Evandro Menezes wrote:
> > The Samsung Exynos M1 implements the ARMv8 ISA and this patch adds
> > support for it through the -mcpu command-line option.
> >
> > The patch was checked on arm-unknown-linux-gnueabihf without new
failures.
> >
> > OK for trunk?
> >
> > -- Evandro Menezes Austin, TX
> >
> > 0001-ARM-Add-option-for-the-Samsung-Exynos-M1-core-for-AR.patch
> >
> >
> > diff --git a/gcc/config/arm/arm-cores.def
> > b/gcc/config/arm/arm-cores.def index b22ea7f..0710a38 100644
> > --- a/gcc/config/arm/arm-cores.def
> > +++ b/gcc/config/arm/arm-cores.def
> > @@ -168,6 +168,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7,
> cortexa7, 7A, FL_LDSCHED |
> > ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED |
> FL_CRC32, cortex_a53)
> > ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED |
> FL_CRC32, cortex_a57)
> > ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, FL_LDSCHED |
> FL_CRC32, cortex_a57)
> > +ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, FL_LDSCHED |
FL_CRC32,
> exynosm1)
>
> There are two problems with this:
> * The 3rd field of ARM_CORE represents the scheduling identifier and
without
> a separate pipeline description for exynosm1 this will just use the
> generic_sched scheduler which performs quite poorly on modern cores.
Would
> you prefer to reuse a pipeline description from one of the pre-existing
ones?
> Look for example at the cortex-a72 definition:
> ARM_CORE("cortex-a72", cortexa72, cortexa57, <...snip>
> here the cortexa57 means 'make scheduling decisions for cortexa57'.
>
> * The final field in ARM_CORE specifies the tuning struct to be used for
this
> core.
> This should be defined in arm.c and have the form 'arm_<ident>_tune, so
for
> your case it should be arm_exynosm1_tune. This isn't defined in your
patch,
> so it won't compile without that. You can write a custom tuning struct
> yourself, or reuse a tuning struct for one of the existing cores, if you'd
> like.
>
> Also, you should add exynosm1 to the switch statement in arm_issue_rate to
> specify the issue rate. I have a patch for next stage1 that should
refactor
> it all into the tuning structs
> (https://gcc.gnu.org/ml/gcc-patches/2014-11/msg02706.html) but until that
> goes in, you should fill in the switch statement there.
>
> Thanks,
> Kyrill
[-- Attachment #2: 0001-ARM-Add-option-for-the-Samsung-Exynos-M1-core.patch --]
[-- Type: application/octet-stream, Size: 4137 bytes --]
From 6c7c17cc3ae52cff4564b1ded097892f12e9c180 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Fri, 20 Mar 2015 15:43:07 -0500
Subject: [PATCH] [ARM] Add option for the Samsung Exynos M1 core.
gcc/
* doc/invoke.texi (ARM/mtune): Add "exynos-m1" as an option.
* config/arm/arm.c (arm_issue_rate): Specify "3" for "exynosm1".
* config/arm/arm-cores.def (exynos-m1): New core.
* config/arm/arm-tune.md: Regenerate.
* config/arm/arm-tables.opt: Add entry for "exynos-m1".
* config/arm/bpabi.h: Likewise.
---
gcc/config/arm/arm-cores.def | 1 +
gcc/config/arm/arm-tables.opt | 3 +++
gcc/config/arm/arm-tune.md | 3 ++-
gcc/config/arm/arm.c | 1 +
gcc/config/arm/bpabi.h | 2 ++
gcc/doc/invoke.texi | 1 +
6 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index b22ea7f..7ade8a1 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -168,6 +168,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, FL_LDSCHED |
ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a53)
ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
+ARM_CORE("exynos-m1", exynosm1, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
ARM_CORE("xgene1", xgene1, xgene1, 8A, FL_LDSCHED, xgene1)
/* V8 big.LITTLE implementations */
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 3450e5b..510e745 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -313,6 +313,9 @@ EnumValue
Enum(processor_type) String(cortex-a72) Value(cortexa72)
EnumValue
+Enum(processor_type) String(exynos-m1) Value(exynosm1)
+
+EnumValue
Enum(processor_type) String(xgene1) Value(xgene1)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index d459f27..8b21d17 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -33,5 +33,6 @@
cortexm7,cortexm4,cortexm3,
marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
cortexa53,cortexa57,cortexa72,
- xgene1,cortexa57cortexa53,cortexa72cortexa53"
+ exynosm1,xgene1,cortexa57cortexa53,
+ cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 50bd3eb..3b2b9a6 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -27209,6 +27209,7 @@ arm_issue_rate (void)
case cortexa15:
case cortexa57:
+ case exynosm1:
return 3;
case cortexm7:
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index c62130d..ceaf2cc 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -73,6 +73,7 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
+ |mcpu=exynos-m1 \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
@@ -97,6 +98,7 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
+ |mcpu=exynos-m1 \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index bf8afad..50caf90 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13202,6 +13202,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m1.small-multiply},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
+@samp{exynos-m1},
@samp{marvell-pj4},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-04-01 0:31 ` Evandro Menezes
@ 2015-04-02 22:19 ` Sebastian Pop
2015-04-02 22:51 ` James Greenhalgh
0 siblings, 1 reply; 11+ messages in thread
From: Sebastian Pop @ 2015-04-02 22:19 UTC (permalink / raw)
To: Evandro Menezes, Ramana Radhakrishnan, James Greenhalgh
Cc: Kyrill Tkachov, GCC Patches
[-- Attachment #1: Type: text/plain, Size: 3283 bytes --]
Hi,
from what I understand, Evandro has addressed the comments from Kyrill.
Are there other problems to be addressed before the patches can go in?
Thanks,
Sebastian
On Tue, Mar 31, 2015 at 7:30 PM, Evandro Menezes <e.menezes@samsung.com> wrote:
> Hi, Kyrill.
>
> At this moment, it suffices to use the same scheduling as Cortex A57, but
> more specific details are to be expected.
>
> I couldn't check the build though, as my Arndale is strange today. As soon
> as it's healthy, I'll check it.
>
> I appreciate your feedback.
>
> --
> Evandro Menezes Austin, TX
>
>
>> -----Original Message-----
>> From: Kyrill Tkachov [mailto:kyrylo.tkachov@arm.com]
>> Sent: Tuesday, March 31, 2015 3:33
>> To: Evandro Menezes; 'GCC Patches'
>> Subject: Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
>>
>> Hi Evandro
>> On 30/03/15 22:51, Evandro Menezes wrote:
>> > The Samsung Exynos M1 implements the ARMv8 ISA and this patch adds
>> > support for it through the -mcpu command-line option.
>> >
>> > The patch was checked on arm-unknown-linux-gnueabihf without new
> failures.
>> >
>> > OK for trunk?
>> >
>> > -- Evandro Menezes Austin, TX
>> >
>> > 0001-ARM-Add-option-for-the-Samsung-Exynos-M1-core-for-AR.patch
>> >
>> >
>> > diff --git a/gcc/config/arm/arm-cores.def
>> > b/gcc/config/arm/arm-cores.def index b22ea7f..0710a38 100644
>> > --- a/gcc/config/arm/arm-cores.def
>> > +++ b/gcc/config/arm/arm-cores.def
>> > @@ -168,6 +168,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7,
>> cortexa7, 7A, FL_LDSCHED |
>> > ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED |
>> FL_CRC32, cortex_a53)
>> > ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED |
>> FL_CRC32, cortex_a57)
>> > ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, FL_LDSCHED |
>> FL_CRC32, cortex_a57)
>> > +ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, FL_LDSCHED |
> FL_CRC32,
>> exynosm1)
>>
>> There are two problems with this:
>> * The 3rd field of ARM_CORE represents the scheduling identifier and
> without
>> a separate pipeline description for exynosm1 this will just use the
>> generic_sched scheduler which performs quite poorly on modern cores.
> Would
>> you prefer to reuse a pipeline description from one of the pre-existing
> ones?
>> Look for example at the cortex-a72 definition:
>> ARM_CORE("cortex-a72", cortexa72, cortexa57, <...snip>
>> here the cortexa57 means 'make scheduling decisions for cortexa57'.
>>
>> * The final field in ARM_CORE specifies the tuning struct to be used for
> this
>> core.
>> This should be defined in arm.c and have the form 'arm_<ident>_tune, so
> for
>> your case it should be arm_exynosm1_tune. This isn't defined in your
> patch,
>> so it won't compile without that. You can write a custom tuning struct
>> yourself, or reuse a tuning struct for one of the existing cores, if you'd
>> like.
>>
>> Also, you should add exynosm1 to the switch statement in arm_issue_rate to
>> specify the issue rate. I have a patch for next stage1 that should
> refactor
>> it all into the tuning structs
>> (https://gcc.gnu.org/ml/gcc-patches/2014-11/msg02706.html) but until that
>> goes in, you should fill in the switch statement there.
>>
>> Thanks,
>> Kyrill
>
[-- Attachment #2: 0001-AArch64-Add-option-for-the-Samsung-Exynos-M1-core-fo.patch --]
[-- Type: application/octet-stream, Size: 3770 bytes --]
From 28ec332a929a6c4ac35a43d350c2ad72f544d2a3 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Thu, 19 Mar 2015 16:18:58 -0500
Subject: [PATCH] [AArch64] Add option for the Samsung Exynos M1 core for
AArch64
gcc/
* doc/invoke.texi (AARCH64/mtune): Add exynos-m1 as an option.
* config/aarch64/aarch64-cores.def (exynos-m1): New core.
* config/aarch64/aarch64-tune.md: Regenerate.
* config/aarch64/aarch64.c (exynosm1_tunings): New variable.
---
gcc/config/aarch64/aarch64-cores.def | 1 +
gcc/config/aarch64/aarch64-tune.md | 2 +-
gcc/config/aarch64/aarch64.c | 18 ++++++++++++++++++
gcc/doc/invoke.texi | 4 ++--
4 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 9b2eca2..d1d29e6 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -37,6 +37,7 @@
AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53)
AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57)
AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57)
+AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1)
AARCH64_CORE("thunderx", thunderx, thunderx, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx)
AARCH64_CORE("xgene1", xgene1, xgene1, 8, AARCH64_FL_FOR_ARCH8, xgene1)
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index c3305f9..7d063e4 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune"
- "cortexa53,cortexa57,cortexa72,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
+ "cortexa53,cortexa57,cortexa72,exynosm1,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index cba3c1a..ca9257c 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -392,6 +392,24 @@ static const struct tune_params cortexa57_tunings =
1 /* vec_reassoc_width. */
};
+static const struct tune_params exynosm1_tunings =
+{
+ &cortexa57_extra_costs,
+ &cortexa57_addrcost_table,
+ &cortexa57_regmove_cost,
+ &cortexa57_vector_cost,
+ 4, /* memmov_cost */
+ 3, /* issue_rate */
+ (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+ | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops */
+ 16, /* function_align. */
+ 8, /* jump_align. */
+ 4, /* loop_align. */
+ 2, /* int_reassoc_width. */
+ 4, /* fp_reassoc_width. */
+ 1 /* vec_reassoc_width. */
+};
+
static const struct tune_params thunderx_tunings =
{
&thunderx_extra_costs,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 4bbd3fc..19606e3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12316,8 +12316,8 @@ architecture.
@opindex mtune
Specify the name of the target processor for which GCC should tune the
performance of the code. Permissible values for this option are:
-@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57},
-@samp{cortex-a72}, @samp{thunderx}, @samp{xgene1}.
+@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
+@samp{exynos-m1}, @samp{thunderx}, @samp{xgene1}.
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible values for this
--
2.1.0.243.g30d45f7
[-- Attachment #3: 0001-ARM-Add-option-for-the-Samsung-Exynos-M1-core.patch --]
[-- Type: application/octet-stream, Size: 4031 bytes --]
From 6c7c17cc3ae52cff4564b1ded097892f12e9c180 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Fri, 20 Mar 2015 15:43:07 -0500
Subject: [PATCH] [ARM] Add option for the Samsung Exynos M1 core.
gcc/
* doc/invoke.texi (ARM/mtune): Add "exynos-m1" as an option.
* config/arm/arm.c (arm_issue_rate): Specify "3" for "exynosm1".
* config/arm/arm-cores.def (exynos-m1): New core.
* config/arm/arm-tune.md: Regenerate.
* config/arm/arm-tables.opt: Add entry for "exynos-m1".
* config/arm/bpabi.h: Likewise.
---
gcc/config/arm/arm-cores.def | 1 +
gcc/config/arm/arm-tables.opt | 3 +++
gcc/config/arm/arm-tune.md | 3 ++-
gcc/config/arm/arm.c | 1 +
gcc/config/arm/bpabi.h | 2 ++
gcc/doc/invoke.texi | 1 +
6 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index b22ea7f..7ade8a1 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -168,6 +168,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, FL_LDSCHED |
ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a53)
ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
+ARM_CORE("exynos-m1", exynosm1, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
ARM_CORE("xgene1", xgene1, xgene1, 8A, FL_LDSCHED, xgene1)
/* V8 big.LITTLE implementations */
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 3450e5b..510e745 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -313,6 +313,9 @@ EnumValue
Enum(processor_type) String(cortex-a72) Value(cortexa72)
EnumValue
+Enum(processor_type) String(exynos-m1) Value(exynosm1)
+
+EnumValue
Enum(processor_type) String(xgene1) Value(xgene1)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index d459f27..8b21d17 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -33,5 +33,6 @@
cortexm7,cortexm4,cortexm3,
marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
cortexa53,cortexa57,cortexa72,
- xgene1,cortexa57cortexa53,cortexa72cortexa53"
+ exynosm1,xgene1,cortexa57cortexa53,
+ cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 50bd3eb..3b2b9a6 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -27209,6 +27209,7 @@ arm_issue_rate (void)
case cortexa15:
case cortexa57:
+ case exynosm1:
return 3;
case cortexm7:
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index c62130d..ceaf2cc 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -73,6 +73,7 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
+ |mcpu=exynos-m1 \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
@@ -97,6 +98,7 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
+ |mcpu=exynos-m1 \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index bf8afad..50caf90 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13202,6 +13202,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m1.small-multiply},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
+@samp{exynos-m1},
@samp{marvell-pj4},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-04-02 22:19 ` Sebastian Pop
@ 2015-04-02 22:51 ` James Greenhalgh
2015-04-03 16:18 ` Sebastian Pop
0 siblings, 1 reply; 11+ messages in thread
From: James Greenhalgh @ 2015-04-02 22:51 UTC (permalink / raw)
To: Sebastian Pop
Cc: Evandro Menezes, Ramana Radhakrishnan, Kyrylo Tkachov, GCC Patches
On Thu, Apr 02, 2015 at 11:19:14PM +0100, Sebastian Pop wrote:
> Hi,
>
> from what I understand, Evandro has addressed the comments from Kyrill.
> Are there other problems to be addressed before the patches can go in?
Trunk is currently in Stage 4 development, these patches are fairly
low-risk, but they are certainly not regression fixes. I'll defer
to port maintainers and release managers for the final say, but in my
opinion it would not be appropriate to commit them until Stage 1
development for GCC 6.0 opens (hopefully in a few weeks).
For the AArch64 patch, I was expecting to see a respin after Junmo's
comment on Wednesday [1].
In particular:
+AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1)
As there has not been a scheduling model contributed for the exynos-m1,
this will use *no* scheduling model on AArch64. This is unlikely to give
good performance.
+static const struct tune_params exynosm1_tunings =
+{
+ &cortexa57_extra_costs,
+ &cortexa57_addrcost_table,
+ &cortexa57_regmove_cost,
+ &cortexa57_vector_cost,
+ 4, /* memmov_cost */
+ 3, /* issue_rate */
+ (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
+ | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops */
+ 16, /* function_align. */
+ 8, /* jump_align. */
+ 4, /* loop_align. */
+ 2, /* int_reassoc_width. */
+ 4, /* fp_reassoc_width. */
+ 1 /* vec_reassoc_width. */
+};
+
As these are identical to the Cortex-A57 tuning, is there any reason to
add them? I'd prefer if we took a copy-on-modify policy for these
tuning structs, only adding them where there is a difference.
Thanks,
James
---
[1]: https://gcc.gnu.org/ml/gcc-patches/2015-04/msg00001.html
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-04-02 22:51 ` James Greenhalgh
@ 2015-04-03 16:18 ` Sebastian Pop
2015-04-03 18:53 ` Ramana Radhakrishnan
0 siblings, 1 reply; 11+ messages in thread
From: Sebastian Pop @ 2015-04-03 16:18 UTC (permalink / raw)
To: James Greenhalgh
Cc: Evandro Menezes, Ramana Radhakrishnan, Kyrylo Tkachov, GCC Patches
[-- Attachment #1: Type: text/plain, Size: 1891 bytes --]
Hi,
On Thu, Apr 2, 2015 at 5:51 PM, James Greenhalgh
<james.greenhalgh@arm.com> wrote:
> Trunk is currently in Stage 4 development, these patches are fairly
> low-risk, but they are certainly not regression fixes. I'll defer
> to port maintainers and release managers for the final say, but in my
> opinion it would not be appropriate to commit them until Stage 1
> development for GCC 6.0 opens (hopefully in a few weeks).
I thought that adding flags for new processors was ok at any time,
even to backport.
> For the AArch64 patch, I was expecting to see a respin after Junmo's
> comment on Wednesday [1].
>
> In particular:
>
> +AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1)
>
> As there has not been a scheduling model contributed for the exynos-m1,
> this will use *no* scheduling model on AArch64. This is unlikely to give
> good performance.
Fixed in the attached patch.
>
> +static const struct tune_params exynosm1_tunings =
> +{
> + &cortexa57_extra_costs,
> + &cortexa57_addrcost_table,
> + &cortexa57_regmove_cost,
> + &cortexa57_vector_cost,
> + 4, /* memmov_cost */
> + 3, /* issue_rate */
> + (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
> + | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops */
> + 16, /* function_align. */
> + 8, /* jump_align. */
> + 4, /* loop_align. */
> + 2, /* int_reassoc_width. */
> + 4, /* fp_reassoc_width. */
> + 1 /* vec_reassoc_width. */
> +};
> +
>
> As these are identical to the Cortex-A57 tuning, is there any reason to
> add them? I'd prefer if we took a copy-on-modify policy for these
> tuning structs, only adding them where there is a difference.
Agreed. Fixed.
I'm testing the two patches with bootstrap and make check on Juno
aarch64-linux and Arndale arm-linux.
Ok for trunk after regstrap passes?
Thanks,
Sebastian
[-- Attachment #2: 0001-ARM-add-option-for-the-Samsung-Exynos-M1-core.patch --]
[-- Type: application/octet-stream, Size: 4049 bytes --]
From 2640078069de4325499887ac84c56694551a3781 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Fri, 20 Mar 2015 15:43:07 -0500
Subject: [PATCH 1/2] [ARM] add option for the Samsung Exynos M1 core
* doc/invoke.texi (ARM/mtune): Add "exynos-m1" as an option.
* config/arm/arm.c (arm_issue_rate): Specify "3" for "exynosm1".
* config/arm/arm-cores.def (exynos-m1): New core.
* config/arm/arm-tune.md: Regenerate.
* config/arm/arm-tables.opt: Add entry for "exynos-m1".
* config/arm/bpabi.h: Likewise.
---
gcc/config/arm/arm-cores.def | 1 +
gcc/config/arm/arm-tables.opt | 3 +++
gcc/config/arm/arm-tune.md | 3 ++-
gcc/config/arm/arm.c | 1 +
gcc/config/arm/bpabi.h | 2 ++
gcc/doc/invoke.texi | 1 +
6 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index b22ea7f..7ade8a1 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -168,6 +168,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, FL_LDSCHED |
ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED | FL_CRC32, cortex_a53)
ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
+ARM_CORE("exynos-m1", exynosm1, cortexa57, 8A, FL_LDSCHED | FL_CRC32, cortex_a57)
ARM_CORE("xgene1", xgene1, xgene1, 8A, FL_LDSCHED, xgene1)
/* V8 big.LITTLE implementations */
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 3450e5b..510e745 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -313,6 +313,9 @@ EnumValue
Enum(processor_type) String(cortex-a72) Value(cortexa72)
EnumValue
+Enum(processor_type) String(exynos-m1) Value(exynosm1)
+
+EnumValue
Enum(processor_type) String(xgene1) Value(xgene1)
EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index d459f27..8b21d17 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -33,5 +33,6 @@
cortexm7,cortexm4,cortexm3,
marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
cortexa53,cortexa57,cortexa72,
- xgene1,cortexa57cortexa53,cortexa72cortexa53"
+ exynosm1,xgene1,cortexa57cortexa53,
+ cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 50bd3eb..3b2b9a6 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -27209,6 +27209,7 @@ arm_issue_rate (void)
case cortexa15:
case cortexa57:
+ case exynosm1:
return 3;
case cortexm7:
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index c62130d..ceaf2cc 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -73,6 +73,7 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
+ |mcpu=exynos-m1 \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
@@ -97,6 +98,7 @@
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
+ |mcpu=exynos-m1 \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c058710..3c1b38c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13211,6 +13211,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m1.small-multiply},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
+@samp{exynos-m1},
@samp{marvell-pj4},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},
--
1.7.9.5
[-- Attachment #3: 0002-AArch64-add-option-for-the-Samsung-Exynos-M1-core-fo.patch --]
[-- Type: application/octet-stream, Size: 2779 bytes --]
From 670d37dd2f5c13bfaec1593fe63dabfe5b6acd1e Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Thu, 19 Mar 2015 16:18:58 -0500
Subject: [PATCH 2/2] [AArch64] add option for the Samsung Exynos M1 core for
AArch64
* doc/invoke.texi (AARCH64/mtune): Add exynos-m1 as an option.
* config/aarch64/aarch64-cores.def (exynos-m1): New core.
* config/aarch64/aarch64-tune.md: Regenerate.
---
gcc/config/aarch64/aarch64-cores.def | 1 +
gcc/config/aarch64/aarch64-tune.md | 2 +-
gcc/doc/invoke.texi | 4 ++--
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 9b2eca2..e46d91b 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -37,6 +37,7 @@
AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53)
AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57)
AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57)
+AARCH64_CORE("exynos-m1", exynosm1, cortexa57, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57)
AARCH64_CORE("thunderx", thunderx, thunderx, 8, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx)
AARCH64_CORE("xgene1", xgene1, xgene1, 8, AARCH64_FL_FOR_ARCH8, xgene1)
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index c3305f9..7d063e4 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune"
- "cortexa53,cortexa57,cortexa72,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
+ "cortexa53,cortexa57,cortexa72,exynosm1,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 3c1b38c..d7ea9b2 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12335,8 +12335,8 @@ architecture.
@opindex mtune
Specify the name of the target processor for which GCC should tune the
performance of the code. Permissible values for this option are:
-@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57},
-@samp{cortex-a72}, @samp{thunderx}, @samp{xgene1}.
+@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
+@samp{exynos-m1}, @samp{thunderx}, @samp{xgene1}.
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible values for this
--
1.7.9.5
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-04-03 16:18 ` Sebastian Pop
@ 2015-04-03 18:53 ` Ramana Radhakrishnan
2015-04-03 21:10 ` James Greenhalgh
0 siblings, 1 reply; 11+ messages in thread
From: Ramana Radhakrishnan @ 2015-04-03 18:53 UTC (permalink / raw)
To: Sebastian Pop
Cc: James Greenhalgh, Evandro Menezes, Ramana Radhakrishnan,
Kyrylo Tkachov, GCC Patches
On Fri, Apr 3, 2015 at 5:17 PM, Sebastian Pop <sebpop@gmail.com> wrote:
> Hi,
>
> On Thu, Apr 2, 2015 at 5:51 PM, James Greenhalgh
> <james.greenhalgh@arm.com> wrote:
>> Trunk is currently in Stage 4 development, these patches are fairly
>> low-risk, but they are certainly not regression fixes. I'll defer
>> to port maintainers and release managers for the final say, but in my
>> opinion it would not be appropriate to commit them until Stage 1
>> development for GCC 6.0 opens (hopefully in a few weeks).
>
> I thought that adding flags for new processors was ok at any time,
> even to backport.
It's usually risk vs reward on a per patch basis and I don't think of
it as a general rule. We've always avoided the CPU tuning backport
rule to the FSF branches. The smaller the CPU tuning patch - the
better it is and in this case I'm comfortable with the patch going in
as it is adding another tuning option, using existing constructs and
is not invasive in the backend.
Ok for the ARM port if no regressions and there are no objections from the RMs.
regards
Ramana
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-04-03 18:53 ` Ramana Radhakrishnan
@ 2015-04-03 21:10 ` James Greenhalgh
2015-04-04 3:03 ` Sebastian Pop
0 siblings, 1 reply; 11+ messages in thread
From: James Greenhalgh @ 2015-04-03 21:10 UTC (permalink / raw)
To: Ramana Radhakrishnan
Cc: Sebastian Pop, Evandro Menezes, Kyrylo Tkachov, GCC Patches
On Fri, Apr 03, 2015 at 07:53:12PM +0100, Ramana Radhakrishnan wrote:
> On Fri, Apr 3, 2015 at 5:17 PM, Sebastian Pop <sebpop@gmail.com> wrote:
> > Hi,
> >
> > On Thu, Apr 2, 2015 at 5:51 PM, James Greenhalgh
> > <james.greenhalgh@arm.com> wrote:
> >> Trunk is currently in Stage 4 development, these patches are fairly
> >> low-risk, but they are certainly not regression fixes. I'll defer
> >> to port maintainers and release managers for the final say, but in my
> >> opinion it would not be appropriate to commit them until Stage 1
> >> development for GCC 6.0 opens (hopefully in a few weeks).
> >
> > I thought that adding flags for new processors was ok at any time,
> > even to backport.
>
> It's usually risk vs reward on a per patch basis and I don't think of
> it as a general rule. We've always avoided the CPU tuning backport
> rule to the FSF branches. The smaller the CPU tuning patch - the
> better it is and in this case I'm comfortable with the patch going in
> as it is adding another tuning option, using existing constructs and
> is not invasive in the backend.
Thanks for the clarification Ramana.
In which case, and now that I've seen that binutils support has also
been accepted, the AArch64 part is OK to commit (assuming no regressions
and no objections from Richard or Jakub).
It would be great if you could follow these up with a patch for
changes.html for GCC 5 for both ARM and AArch64.
Cheers,
James
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-04-03 21:10 ` James Greenhalgh
@ 2015-04-04 3:03 ` Sebastian Pop
2015-04-04 6:26 ` Richard Biener
0 siblings, 1 reply; 11+ messages in thread
From: Sebastian Pop @ 2015-04-04 3:03 UTC (permalink / raw)
To: James Greenhalgh, Richard Guenther, Jakub Jelinek
Cc: Ramana Radhakrishnan, Evandro Menezes, Kyrylo Tkachov, GCC Patches
[-- Attachment #1: Type: text/plain, Size: 1717 bytes --]
On Fri, Apr 3, 2015 at 4:09 PM, James Greenhalgh
<james.greenhalgh@arm.com> wrote:
> On Fri, Apr 03, 2015 at 07:53:12PM +0100, Ramana Radhakrishnan wrote:
>> On Fri, Apr 3, 2015 at 5:17 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>> > Hi,
>> >
>> > On Thu, Apr 2, 2015 at 5:51 PM, James Greenhalgh
>> > <james.greenhalgh@arm.com> wrote:
>> >> Trunk is currently in Stage 4 development, these patches are fairly
>> >> low-risk, but they are certainly not regression fixes. I'll defer
>> >> to port maintainers and release managers for the final say, but in my
>> >> opinion it would not be appropriate to commit them until Stage 1
>> >> development for GCC 6.0 opens (hopefully in a few weeks).
>> >
>> > I thought that adding flags for new processors was ok at any time,
>> > even to backport.
>>
>> It's usually risk vs reward on a per patch basis and I don't think of
>> it as a general rule. We've always avoided the CPU tuning backport
>> rule to the FSF branches. The smaller the CPU tuning patch - the
>> better it is and in this case I'm comfortable with the patch going in
>> as it is adding another tuning option, using existing constructs and
>> is not invasive in the backend.
>
> Thanks for the clarification Ramana.
>
> In which case, and now that I've seen that binutils support has also
> been accepted, the AArch64 part is OK to commit (assuming no regressions
> and no objections from Richard or Jakub).
I will wait to hear from Richi or Jakub before committing the two patches.
>
> It would be great if you could follow these up with a patch for
> changes.html for GCC 5 for both ARM and AArch64.
Attached. I will commit this after the two patches adding the exynos-m1 flags.
Thanks,
Sebastian
[-- Attachment #2: changes.diff --]
[-- Type: text/plain, Size: 2126 bytes --]
*** changes.html.~1.92.~ 2015-03-27 09:42:10.000000000 -0500
--- changes.html 2015-04-03 21:57:33.550001606 -0500
***************
*** 585,591 ****
(<code>cortex-a72</code>) and initial support for its big.LITTLE
combination with the ARM Cortex-A53 (<code>cortex-a72.cortex-a53</code>),
Cavium ThunderX (<code>thunderx</code>), Applied Micro X-Gene 1
! (<code>xgene1</code>).
The GCC identifiers can be used
as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
for example: <code>-mcpu=xgene1</code> or
--- 585,591 ----
(<code>cortex-a72</code>) and initial support for its big.LITTLE
combination with the ARM Cortex-A53 (<code>cortex-a72.cortex-a53</code>),
Cavium ThunderX (<code>thunderx</code>), Applied Micro X-Gene 1
! (<code>xgene1</code>), and Samsung Exynos M1 (<code>exynos-m1</code>).
The GCC identifiers can be used
as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
for example: <code>-mcpu=xgene1</code> or
***************
*** 624,630 ****
(<code>cortex-a72</code>) and initial support for its big.LITTLE
combination with the ARM Cortex-A53 (<code>cortex-a72.cortex-a53</code>),
ARM Cortex-M7 (<code>cortex-m7</code>), Applied Micro X-Gene 1
! (<code>xgene1</code>). The GCC identifiers can be used
as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
for example: <code>-mcpu=xgene1</code> or
<code>-mtune=cortex-a72.cortex-a53</code>.
--- 624,631 ----
(<code>cortex-a72</code>) and initial support for its big.LITTLE
combination with the ARM Cortex-A53 (<code>cortex-a72.cortex-a53</code>),
ARM Cortex-M7 (<code>cortex-m7</code>), Applied Micro X-Gene 1
! (<code>xgene1</code>), and Samsung Exynos M1 (<code>exynos-m1</code>).
! The GCC identifiers can be used
as arguments to the <code>-mcpu</code> or <code>-mtune</code> options,
for example: <code>-mcpu=xgene1</code> or
<code>-mtune=cortex-a72.cortex-a53</code>.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-04-04 3:03 ` Sebastian Pop
@ 2015-04-04 6:26 ` Richard Biener
2015-04-06 19:29 ` Sebastian Pop
0 siblings, 1 reply; 11+ messages in thread
From: Richard Biener @ 2015-04-04 6:26 UTC (permalink / raw)
To: Sebastian Pop, James Greenhalgh, Jakub Jelinek
Cc: Ramana Radhakrishnan, Evandro Menezes, Kyrylo Tkachov, GCC Patches
On April 4, 2015 5:03:14 AM GMT+02:00, Sebastian Pop <sebpop@gmail.com> wrote:
>On Fri, Apr 3, 2015 at 4:09 PM, James Greenhalgh
><james.greenhalgh@arm.com> wrote:
>> On Fri, Apr 03, 2015 at 07:53:12PM +0100, Ramana Radhakrishnan wrote:
>>> On Fri, Apr 3, 2015 at 5:17 PM, Sebastian Pop <sebpop@gmail.com>
>wrote:
>>> > Hi,
>>> >
>>> > On Thu, Apr 2, 2015 at 5:51 PM, James Greenhalgh
>>> > <james.greenhalgh@arm.com> wrote:
>>> >> Trunk is currently in Stage 4 development, these patches are
>fairly
>>> >> low-risk, but they are certainly not regression fixes. I'll defer
>>> >> to port maintainers and release managers for the final say, but
>in my
>>> >> opinion it would not be appropriate to commit them until Stage 1
>>> >> development for GCC 6.0 opens (hopefully in a few weeks).
>>> >
>>> > I thought that adding flags for new processors was ok at any time,
>>> > even to backport.
>>>
>>> It's usually risk vs reward on a per patch basis and I don't think
>of
>>> it as a general rule. We've always avoided the CPU tuning backport
>>> rule to the FSF branches. The smaller the CPU tuning patch - the
>>> better it is and in this case I'm comfortable with the patch going
>in
>>> as it is adding another tuning option, using existing constructs and
>>> is not invasive in the backend.
>>
>> Thanks for the clarification Ramana.
>>
>> In which case, and now that I've seen that binutils support has also
>> been accepted, the AArch64 part is OK to commit (assuming no
>regressions
>> and no objections from Richard or Jakub).
>
>I will wait to hear from Richi or Jakub before committing the two
>patches.
OK.
Richard.
>>
>> It would be great if you could follow these up with a patch for
>> changes.html for GCC 5 for both ARM and AArch64.
>
>Attached. I will commit this after the two patches adding the
>exynos-m1 flags.
>
>Thanks,
>Sebastian
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] [ARM] Add support for the Samsung Exynos M1 processor
2015-04-04 6:26 ` Richard Biener
@ 2015-04-06 19:29 ` Sebastian Pop
0 siblings, 0 replies; 11+ messages in thread
From: Sebastian Pop @ 2015-04-06 19:29 UTC (permalink / raw)
To: Richard Biener
Cc: James Greenhalgh, Jakub Jelinek, Ramana Radhakrishnan,
Evandro Menezes, Kyrylo Tkachov, GCC Patches
On Sat, Apr 4, 2015 at 1:25 AM, Richard Biener <rguenther@suse.de> wrote:
> On April 4, 2015 5:03:14 AM GMT+02:00, Sebastian Pop <sebpop@gmail.com> wrote:
>>On Fri, Apr 3, 2015 at 4:09 PM, James Greenhalgh
>><james.greenhalgh@arm.com> wrote:
>>> On Fri, Apr 03, 2015 at 07:53:12PM +0100, Ramana Radhakrishnan wrote:
>>>> On Fri, Apr 3, 2015 at 5:17 PM, Sebastian Pop <sebpop@gmail.com>
>>wrote:
>>>> > Hi,
>>>> >
>>>> > On Thu, Apr 2, 2015 at 5:51 PM, James Greenhalgh
>>>> > <james.greenhalgh@arm.com> wrote:
>>>> >> Trunk is currently in Stage 4 development, these patches are
>>fairly
>>>> >> low-risk, but they are certainly not regression fixes. I'll defer
>>>> >> to port maintainers and release managers for the final say, but
>>in my
>>>> >> opinion it would not be appropriate to commit them until Stage 1
>>>> >> development for GCC 6.0 opens (hopefully in a few weeks).
>>>> >
>>>> > I thought that adding flags for new processors was ok at any time,
>>>> > even to backport.
>>>>
>>>> It's usually risk vs reward on a per patch basis and I don't think
>>of
>>>> it as a general rule. We've always avoided the CPU tuning backport
>>>> rule to the FSF branches. The smaller the CPU tuning patch - the
>>>> better it is and in this case I'm comfortable with the patch going
>>in
>>>> as it is adding another tuning option, using existing constructs and
>>>> is not invasive in the backend.
>>>
>>> Thanks for the clarification Ramana.
>>>
>>> In which case, and now that I've seen that binutils support has also
>>> been accepted, the AArch64 part is OK to commit (assuming no
>>regressions
>>> and no objections from Richard or Jakub).
>>
>>I will wait to hear from Richi or Jakub before committing the two
>>patches.
>
> OK.
>
Committed r221883, r221884, and committed the wwwdocs patch to
gcc-5/changes.html
Sebastian
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-04-06 19:29 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-30 21:52 [PATCH] [ARM] Add support for the Samsung Exynos M1 processor Evandro Menezes
2015-03-31 8:33 ` Kyrill Tkachov
2015-04-01 0:31 ` Evandro Menezes
2015-04-02 22:19 ` Sebastian Pop
2015-04-02 22:51 ` James Greenhalgh
2015-04-03 16:18 ` Sebastian Pop
2015-04-03 18:53 ` Ramana Radhakrishnan
2015-04-03 21:10 ` James Greenhalgh
2015-04-04 3:03 ` Sebastian Pop
2015-04-04 6:26 ` Richard Biener
2015-04-06 19:29 ` Sebastian Pop
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