* [PATCH] RISC-V: Removed misleading comments in testcases
@ 2023-09-18 12:29 Lehua Ding
2023-09-18 12:30 ` juzhe.zhong
0 siblings, 1 reply; 3+ messages in thread
From: Lehua Ding @ 2023-09-18 12:29 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, kito.cheng, rdapp.gcc, palmer, jeffreyalaw, lehua.ding
This patch removed the misleading comments in testcases since we
support fold min(int, poly) to constant by this patch
(https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629651.html).
Thereby the csrr will not appear inside the assembly code, even if there
is no support for some VLS vector patterns.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/div-1.c: Removed comments.
* gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto.
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c | 1 -
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
index 40224c69458..e36fa9decfd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
@@ -54,5 +54,4 @@ DEF_OP_VV (div, 256, int64_t, /)
DEF_OP_VV (div, 512, int64_t, /)
/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
-/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division. */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
index b34a349949b..db2295b2dd6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
@@ -54,5 +54,4 @@ DEF_OP_VV (shift, 256, int64_t, <<)
DEF_OP_VV (shift, 512, int64_t, <<)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 41 } } */
-/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division. */
/* { dg-final { scan-assembler-not {csrr} } } */
--
2.36.3
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Removed misleading comments in testcases
2023-09-18 12:29 [PATCH] RISC-V: Removed misleading comments in testcases Lehua Ding
@ 2023-09-18 12:30 ` juzhe.zhong
2023-09-18 12:31 ` Lehua Ding
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-09-18 12:30 UTC (permalink / raw)
To: 丁乐华, gcc-patches
Cc: kito.cheng, Robin Dapp, palmer, jeffreyalaw, 丁乐华
[-- Attachment #1: Type: text/plain, Size: 2327 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: Lehua Ding
Date: 2023-09-18 20:29
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Removed misleading comments in testcases
This patch removed the misleading comments in testcases since we
support fold min(int, poly) to constant by this patch
(https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629651.html).
Thereby the csrr will not appear inside the assembly code, even if there
is no support for some VLS vector patterns.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/div-1.c: Removed comments.
* gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto.
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c | 1 -
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
index 40224c69458..e36fa9decfd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
@@ -54,5 +54,4 @@ DEF_OP_VV (div, 256, int64_t, /)
DEF_OP_VV (div, 512, int64_t, /)
/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
-/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division. */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
index b34a349949b..db2295b2dd6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
@@ -54,5 +54,4 @@ DEF_OP_VV (shift, 256, int64_t, <<)
DEF_OP_VV (shift, 512, int64_t, <<)
/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 41 } } */
-/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division. */
/* { dg-final { scan-assembler-not {csrr} } } */
--
2.36.3
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Removed misleading comments in testcases
2023-09-18 12:30 ` juzhe.zhong
@ 2023-09-18 12:31 ` Lehua Ding
0 siblings, 0 replies; 3+ messages in thread
From: Lehua Ding @ 2023-09-18 12:31 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng, Robin Dapp, palmer, jeffreyalaw
Committed, thanks Juzhe.
On 2023/9/18 20:30, juzhe.zhong@rivai.ai wrote:
> LGTM
>
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
> *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
> *Date:* 2023-09-18 20:29
> *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
> *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
> <mailto:kito.cheng@gmail.com>; rdapp.gcc
> <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
> jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
> <mailto:lehua.ding@rivai.ai>
> *Subject:* [PATCH] RISC-V: Removed misleading comments in testcases
> This patch removed the misleading comments in testcases since we
> support fold min(int, poly) to constant by this patch
> (https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629651.html).
> Thereby the csrr will not appear inside the assembly code, even if there
> is no support for some VLS vector patterns.
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/rvv/autovec/vls/div-1.c: Removed comments.
> * gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto.
> ---
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c | 1 -
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c | 1 -
> 2 files changed, 2 deletions(-)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
> index 40224c69458..e36fa9decfd 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
> @@ -54,5 +54,4 @@ DEF_OP_VV (div, 256, int64_t, /)
> DEF_OP_VV (div, 512, int64_t, /)
> /* { dg-final { scan-assembler-times
> {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
> -/* TODO: Ideally, we should make sure there is no "csrr vlenb".
> However, we still have 'csrr vlenb' for some cases since we don't
> support VLS mode conversion which are needed by division. */
> /* { dg-final { scan-assembler-not {csrr} } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
> index b34a349949b..db2295b2dd6 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
> @@ -54,5 +54,4 @@ DEF_OP_VV (shift, 256, int64_t, <<)
> DEF_OP_VV (shift, 512, int64_t, <<)
> /* { dg-final { scan-assembler-times
> {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 41 } } */
> -/* TODO: Ideally, we should make sure there is no "csrr vlenb".
> However, we still have 'csrr vlenb' for some cases since we don't
> support VLS mode conversion which are needed by division. */
> /* { dg-final { scan-assembler-not {csrr} } } */
> --
> 2.36.3
>
--
Best,
Lehua
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-09-18 12:30 ` juzhe.zhong
2023-09-18 12:31 ` Lehua Ding
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