From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id E72563858D1E for ; Fri, 20 Oct 2023 02:20:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E72563858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E72563858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=13.245.218.24 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697768455; cv=none; b=nuYjZP+NkA3TylBZV7+FPMDWYUkouJPoXhpLv2kTcrncQPdagtQdOebOGUXkALvRVLMo/OiPGMuCnC3HjenGUYdyPHhyG16kg2Bt7d1jpxdsTwAvKgJ8nmWCTG4pRHQW7WUcDN8WGJCrscgKloGHTb8Z0nwcb4CKwO9j8diLc1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697768455; c=relaxed/simple; bh=BpA11T31/jrNtgy03TV7Gb9zusQ6kiEivCAYND7dJ48=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=WvU+LHzVvAWuwHgTq9iz0lnQqw8C/GKHWGzka4ZARgUSKR6KPw4uWkRyCgGY+MVdPzh2lTZat19jX5sD/qQH/e41z8K+SPVCemH12aZHH5dchQlDH5uvPsTepaxr+L5qNv7BQiVUwfOu7XNNej8bH6EZb4NNIIaSYmjCfz84IFw= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp68t1697768442tk4m4bes Received: from [10.101.11.9] ( [113.104.225.121]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 20 Oct 2023 10:20:41 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: NV69rQnjVY6shBPQIOCu/6Z3n7v923wR20gq+e98Vgq5dpingSmCnaojgVmDu L9pnLiOkgY2KvSlT+z6S9/J/oTPHdUcJ2w1oocbOUjATVCGANGqM53SgC9GCZwQeBYcbTeA 4FkZnOTx7y9UEZV1c3r9KRg3XYmfFg06LqgTW4BxXqum2bictcQM4QEx5ixgzVdkWKEZDGv gB3duH0+Sr3ubGvTnQsYKVhfNYFFlMJ4uVSK1ukrtSYauvh/KPGyXzGTJETSFNkcS9jMU+z kRRulBJ+1LMreyRjhBnDA/W14TzSQv/WrnlLp57Ur4xL7VuWzvWIza2mtwqn0q/CmYXDIhN Feuv3/Uz8aeW6TGznp+iQzYCORtZiI5WftwNGXsy9fhrMwBd2vBOkHIb3vvXg== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 2077029658923013742 Message-ID: Date: Fri, 20 Oct 2023 10:20:41 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass Content-Language: en-US To: Patrick O'Neill , =?UTF-8?B?6ZKf5bGF5ZOy?= , gcc-patches Cc: "kito.cheng" , "rdapp.gcc" , palmer , Jeff Law References: <20231019083333.2052340-1-lehua.ding@rivai.ai> <17037AC761126CB1+2023101916505449794275@rivai.ai> <010dab03-b995-be03-8a73-241d7595452d@rivosinc.com> From: Lehua Ding In-Reply-To: <010dab03-b995-be03-8a73-241d7595452d@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,BODY_8BITS,FORGED_MUA_MOZILLA,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Patrick, Thanks a lot for helping to test these patchs! On 2023/10/20 2:04, Patrick O'Neill wrote: > I tested it this morning on my machine and it passed! > > Tested against: > 04d6c74564b7eb51660a00b35353aeab706b5a50 > > Using targets: > glibc rv32gcv qemu > glibc rv64gcv qemu > > This patch series does not introduce any new failures. > > Here's a list of *resolved* failures by this patch series: > rv64gcv: > FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer > -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test > FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test > > rv32gcv: > FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test > FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer > -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test > FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test > > Thanks for the quick revision Lehua! > > Tested-by: Patrick O'Neill > > Patrick > > On 10/19/23 01:50, 钟居哲 wrote: >> LGTM now. But wait for Patrick CI testing. >> >> Hi, @Patrick. Could you apply this patch and trigger CI in your >> github  so that we can see the full running result. >> >> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub >> >> >> ------------------------------------------------------------------------ >> juzhe.zhong@rivai.ai >> >> *From:* Lehua Ding >> *Date:* 2023-10-19 16:33 >> *To:* gcc-patches >> *CC:* juzhe.zhong ; kito.cheng >> ; rdapp.gcc >> ; palmer ; >> jeffreyalaw ; lehua.ding >> >> *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass >> This patch refactors and cleanups the vsetvl pass in order to make >> the code >> easier to modify and understand. This patch does several things: >> 1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3 >> only maintain >>    and modify this virtual CFG. Phase 4 performs insertion, >> modification and >>    deletion of vsetvl insns based on the virtual CFG. The Basic >> block in the >>    virtual CFG is called vsetvl_block_info and the vsetvl >> information inside >>    is called vsetvl_info. >> 2. Combine Phase 1 and 2 into a single Phase 1 and unified the >> demand system, >>    this Phase only fuse local vsetvl info in forward direction. >> 3. Refactor Phase 3, change the logic for determining whether to >> uplift vsetvl >>    info to a pred basic block to a more unified method that there >> is a vsetvl >>    info in the vsetvl defintion reaching in compatible with it. >> 4. Place all modification operations to the RTL in Phase 4 and >> Phase 5. >>    Phase 4 is responsible for inserting, modifying and deleting vsetvl >>    instructions based on fully optimized vsetvl infos. Phase 5 >> removes the avl >>    operand from the RVV instruction and removes the unused dest >> operand >>    register from the vsetvl insns. >> These modifications resulted in some testcases needing to be >> updated. The reasons >> for updating are summarized below: >> 1. more optimized >> vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/ >>    vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/ >> avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c >> 2. less unnecessary fusion >> avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c >> 3. local fuse direction (backward -> forward) >>    scalar_move-1.c/ >> 4. add some bugfix testcases. >>    pr111037-3.c/pr111037-4.c >>    avl_single-89.c >> PR target/111037 >> PR target/111234 >> PR target/111725 >> Lehua Ding (11): >>   RISC-V: P1: Refactor >> avl_info/vl_vtype_info/vector_insn_info/vector_block_info >>   RISC-V: P2: Refactor and cleanup demand system >>   RISC-V: P3: Refactor vector_infos_manager >>   RISC-V: P4: move method from pass_vsetvl to pre_vsetvl >>   RISC-V: P5: combine phase 1 and 2 >>   RISC-V: P6: Add computing reaching definition data flow >>   RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class >>   RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization >>   RISC-V: P9: Cleanup and reorganize helper functions >>   RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def >>   RISC-V: P11: Adjust and add testcases >> gcc/config/riscv/riscv-vsetvl.cc              | 6502 +++++++---------- >> gcc/config/riscv/riscv-vsetvl.def             |  641 +- >> gcc/config/riscv/riscv-vsetvl.h               |  488 -- >> gcc/config/riscv/t-riscv                      |    2 +- >> .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +- >> .../riscv/rvv/vsetvl/avl_single-104.c         |   35 + >> .../riscv/rvv/vsetvl/avl_single-105.c         |   23 + >> .../riscv/rvv/vsetvl/avl_single-106.c         |   34 + >> .../riscv/rvv/vsetvl/avl_single-107.c         |   41 + >> .../riscv/rvv/vsetvl/avl_single-108.c         |   41 + >> .../riscv/rvv/vsetvl/avl_single-109.c         |   45 + >> .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +- >> .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +- >> .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +- >> .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +- >> .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +- >> .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +- >> .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +- >> .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +- >> .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0 >> .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0 >> .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 + >> .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 + >> .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +- >> .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +- >> .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 - >> .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +- >> .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +- >> 30 files changed, 3263 insertions(+), 4692 deletions(-) >> delete mode 100644 gcc/config/riscv/riscv-vsetvl.h >> create mode 100644 >> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c >> create mode 100644 >> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c >> create mode 100644 >> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c >> create mode 100644 >> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c >> create mode 100644 >> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c >> create mode 100644 >> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c >> rename gcc/testsuite/gcc.target/riscv/rvv/{base => >> vsetvl}/pr111037-1.c (100%) >> rename gcc/testsuite/gcc.target/riscv/rvv/{base => >> vsetvl}/pr111037-2.c (100%) >> create mode 100644 >> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c >> create mode 100644 >> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c >> -- >> 2.36.3 >> -- Best, Lehua (RiVAI) lehua.ding@rivai.ai