[vect] Ask for review and approving the patch about vect and loongson

[vect] Ask for review and approving the patch about vect and loongson

[Eric Fisher]

[-- Attachment #1: Type: text/plain, Size: 2504 bytes --]

Hello,

I put all of the patches I sent to the mailing list these days here
together. I would be appreciated if anyone could take time to review
or give suggestions. Here is some description about the changes.

1. Remove the duplicated item vect_int_mult in gccint doc.

In gccint, 7.2.3.3 Vector-specific attributes, there are two items
talking about vect_int_mult:

vect_int_mult
   Target supports a vector widening multiplication of short operands
into an int result, or supports promotion (unpacking) from short to
int and a non-widening multiplication of int.

vect_int_mult
   Target supports vector int multiplication.

The first one must be a mistake.

2. Fix directives order in a testcase

/* { dg-do compile } */
/* { dg-require-effective-target vect_float } */

According to the gccint, dg-require-effective-target directive must
appear after any dg-do directive in the test and before any
dg-additional-sources directive. This patch moves
dg-require-effective-target after dg-do in fast-math-vect-reduc-8.c.

3. Modify vect.exp to go on running the testsuite when the target is mips*.

...
} elseif { [istarget "mips*-*-*"]
           && [check_effective_target_mpaired_single]
           && [check_effective_target_nomips16] } {
    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
    set dg-do-what-default run
...
} else {
    return
}

The original logic will fall into the 'else' fragment when the target
doesn't support paired-single, hence 'return'. The change will make
the test go on even the target doesn't support paired-single such as
loongson2f which has SIMD instructions.

4. Modify target-supports.exp to verify loongson target in vector
specific attributes.

This patch will modify the target-support.exp to enable vect_int,
vect_shift, vect_no_int_max, vect_short_mult and vect_no_align for
loongson target. So that the auto-vectorization tests will be done for
loongson.

5. Modify loongson.md to add standard patterns to generate SIMD automatically.

Add define_expand for mulm3 (VH), ashrm3 (VWH), lshrm3 (VWH), so that
the vector insn can be generated, and the loop vector can do the
vectorization for these situation, for an example vect-shift-1.c.


The patch is tested on loongson2f, and the result is:

		=== gcc Summary ===

# of expected passes		1020
# of unexpected failures	6
# of unexpected successes	15
# of expected failures		91
# of unsupported tests		142
/home/xmj/tools/build-trunk/gcc/xgcc  version 4.6.0 20100706
(experimental) (GCC)


Best regards,
Eric

[-- Attachment #2: vect.patch --]
[-- Type: text/x-diff, Size: 5756 bytes --]

Index: doc/sourcebuild.texi
===================================================================
--- doc/sourcebuild.texi	(revision 161865)
+++ doc/sourcebuild.texi	(working copy)
@@ -1324,11 +1324,6 @@ Target supports hardware vectors of @cod
 @item vect_int
 Target supports hardware vectors of @code{int}.
 
-@item vect_int_mult
-Target supports a vector widening multiplication of @code{short} operands
-into an @code{int} result, or supports promotion (unpacking) from
-@code{short} to @code{int} and a non-widening multiplication of @code{int}.
-
 @item vect_long
 Target supports hardware vectors of @code{long}.
 
Index: testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c
===================================================================
--- testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c	(revision 161865)
+++ testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c	(working copy)
@@ -1,5 +1,5 @@
-/* { dg-require-effective-target vect_float } */
 /* { dg-do compile } */
+/* { dg-require-effective-target vect_float } */
 
 #include "tree-vect.h"
 
Index: testsuite/gcc.dg/vect/vect.exp
===================================================================
--- testsuite/gcc.dg/vect/vect.exp	(revision 161865)
+++ testsuite/gcc.dg/vect/vect.exp	(working copy)
@@ -76,10 +76,10 @@ if  [istarget "powerpc-*paired*"]  {
     } else {
 	set dg-do-what-default compile
     }
-} elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+} elseif { [istarget "mips*-*-*"] && [check_effective_target_nomips16] } {
+    if { [check_effective_target_mpaired_single] } {
+        lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    }
     set dg-do-what-default run
 } elseif [istarget "sparc*-*-*"] {
     lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
Index: testsuite/lib/target-supports.exp
===================================================================
--- testsuite/lib/target-supports.exp	(revision 161865)
+++ testsuite/lib/target-supports.exp	(working copy)
@@ -1493,7 +1493,8 @@ proc check_effective_target_vect_int { }
 	      || [istarget sparc*-*-*]
 	      || [istarget alpha*-*-*]
 	      || [istarget ia64-*-*] 
-	      || [check_effective_target_arm32] } {
+	      || [check_effective_target_arm32]
+              || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_int_saved 1
 	}
     }
@@ -2029,7 +2030,8 @@ proc check_effective_target_vect_shift {
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
-	     || [check_effective_target_arm32] } {
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_shift_saved 1
 	}
     }
@@ -2143,7 +2145,8 @@ proc check_effective_target_vect_no_int_
 	set et_vect_no_int_max_saved 0
 	if { [istarget sparc*-*-*]
 	     || [istarget spu-*-*]
-	     || [istarget alpha*-*-*] } {
+	     || [istarget alpha*-*-*]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_int_max_saved 1
 	}
     }
@@ -2516,7 +2519,8 @@ proc check_effective_target_vect_no_alig
 	if { [istarget mipsisa64*-*-*]
 	     || [istarget sparc*-*-*]
 	     || [istarget ia64-*-*]
-	     || [check_effective_target_arm32] } { 
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_align_saved 1
 	}
     }
@@ -2707,7 +2711,8 @@ proc check_effective_target_vect_short_m
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
              || [istarget powerpc*-*-*]
-             || [check_effective_target_arm32] } {
+             || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_short_mult_saved 1
 	}
     }
Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 161865)
+++ config/mips/loongson.md	(working copy)
@@ -352,6 +352,16 @@
   "pmulh<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
 
+;; Standard pattern mulm3
+(define_expand "mul<mode>3"
+  [(set (match_operand:VH 0 "register_operand" "=f")
+        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
+                    (match_operand:VH 2 "register_operand" "f")]
+                   UNSPEC_LOONGSON_PMULL))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
+
 ;; Multiply signed integers and store low result.
 (define_insn "loongson_pmull<V_suffix>"
   [(set (match_operand:VH 0 "register_operand" "=f")
@@ -421,6 +431,14 @@
   "psll<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
 
+;; Standard pattern ashrm3
+(define_expand "ashr<mode>3"
+  [(set (match_operand:VWH 0 "register_operand" "=f")
+        (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
+                      (match_operand:SI 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
 ;; Shift right arithmetic.
 (define_insn "loongson_psra<V_suffix>"
   [(set (match_operand:VWH 0 "register_operand" "=f")
@@ -430,6 +448,14 @@
   "psra<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fdiv")])
 
+;; Standard pattern lshrm3
+(define_expand "lshr<mode>3"
+  [(set (match_operand:VWH 0 "register_operand" "=f")
+        (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
+                      (match_operand:SI 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
 ;; Shift right logical.
 (define_insn "loongson_psrl<V_suffix>"
   [(set (match_operand:VWH 0 "register_operand" "=f")

Re: [vect] Ask for review and approving the patch about vect and loongson

[Richard Guenther]

On Fri, Jul 9, 2010 at 4:11 AM, Eric Fisher <joefoxreal@gmail.com> wrote:
> Hello,
>
> I put all of the patches I sent to the mailing list these days here
> together. I would be appreciated if anyone could take time to review
> or give suggestions. Here is some description about the changes.
>
> 1. Remove the duplicated item vect_int_mult in gccint doc.
>
> In gccint, 7.2.3.3 Vector-specific attributes, there are two items
> talking about vect_int_mult:
>
> vect_int_mult
>   Target supports a vector widening multiplication of short operands
> into an int result, or supports promotion (unpacking) from short to
> int and a non-widening multiplication of int.
>
> vect_int_mult
>   Target supports vector int multiplication.
>
> The first one must be a mistake.
>
> 2. Fix directives order in a testcase
>
> /* { dg-do compile } */
> /* { dg-require-effective-target vect_float } */
>
> According to the gccint, dg-require-effective-target directive must
> appear after any dg-do directive in the test and before any
> dg-additional-sources directive. This patch moves
> dg-require-effective-target after dg-do in fast-math-vect-reduc-8.c.
>
> 3. Modify vect.exp to go on running the testsuite when the target is mips*.
>
> ...
> } elseif { [istarget "mips*-*-*"]
>           && [check_effective_target_mpaired_single]
>           && [check_effective_target_nomips16] } {
>    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
>    set dg-do-what-default run
> ...
> } else {
>    return
> }
>
> The original logic will fall into the 'else' fragment when the target
> doesn't support paired-single, hence 'return'. The change will make
> the test go on even the target doesn't support paired-single such as
> loongson2f which has SIMD instructions.
>
> 4. Modify target-supports.exp to verify loongson target in vector
> specific attributes.
>
> This patch will modify the target-support.exp to enable vect_int,
> vect_shift, vect_no_int_max, vect_short_mult and vect_no_align for
> loongson target. So that the auto-vectorization tests will be done for
> loongson.
>
> 5. Modify loongson.md to add standard patterns to generate SIMD automatically.
>
> Add define_expand for mulm3 (VH), ashrm3 (VWH), lshrm3 (VWH), so that
> the vector insn can be generated, and the loop vector can do the
> vectorization for these situation, for an example vect-shift-1.c.
>
>
> The patch is tested on loongson2f, and the result is:

How about splitting the patch?

Richard.

>                === gcc Summary ===
>
> # of expected passes            1020
> # of unexpected failures        6
> # of unexpected successes       15
> # of expected failures          91
> # of unsupported tests          142
> /home/xmj/tools/build-trunk/gcc/xgcc  version 4.6.0 20100706
> (experimental) (GCC)
>
>
> Best regards,
> Eric
>

Re: [vect] Ask for review and approving the patch about vect and loongson

[Eric Fisher]

[-- Attachment #1: Type: text/plain, Size: 623 bytes --]

2010/7/9 Richard Guenther <richard.guenther@gmail.com>:
>
> How about splitting the patch?
>
> Richard.
>

Thanks. I put the patch separately now. And the ChageLogs,

gcc/ChangeLog
  * sourcebuild.texi: Remove duplicated item vect_int_mult.
  * loongson.md: Add define_expand for standard names mulm3 (VH),
ashrm3 (VWH), lshrm3 (VWH) to generate SIMD automatically.

testsuite/ChangeLog
  * fast-math-vect-reduc-8.c: Move dg-require-effective-target after dg-do.
  * vect.exp: Go on running the testsuite when the target is mips*
  * target-supports.exp: Check loongson target in vector specific attributes.


Thanks,
Eric

[-- Attachment #2: sourcebuild.patch --]
[-- Type: text/x-diff, Size: 621 bytes --]

Index: doc/sourcebuild.texi
===================================================================
--- doc/sourcebuild.texi	(revision 161865)
+++ doc/sourcebuild.texi	(working copy)
@@ -1324,11 +1324,6 @@ Target supports hardware vectors of @cod
 @item vect_int
 Target supports hardware vectors of @code{int}.
 
-@item vect_int_mult
-Target supports a vector widening multiplication of @code{short} operands
-into an @code{int} result, or supports promotion (unpacking) from
-@code{short} to @code{int} and a non-widening multiplication of @code{int}.
-
 @item vect_long
 Target supports hardware vectors of @code{long}.
 

[-- Attachment #3: fast-math-vect-reduc-8.patch --]
[-- Type: text/x-diff, Size: 426 bytes --]

Index: testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c
===================================================================
--- testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c	(revision 161865)
+++ testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c	(working copy)
@@ -1,5 +1,5 @@
-/* { dg-require-effective-target vect_float } */
 /* { dg-do compile } */
+/* { dg-require-effective-target vect_float } */
 
 #include "tree-vect.h"
 

[-- Attachment #4: vect.patch --]
[-- Type: text/x-diff, Size: 817 bytes --]

Index: testsuite/gcc.dg/vect/vect.exp
===================================================================
--- testsuite/gcc.dg/vect/vect.exp	(revision 161865)
+++ testsuite/gcc.dg/vect/vect.exp	(working copy)
@@ -76,10 +76,10 @@ if  [istarget "powerpc-*paired*"]  {
     } else {
 	set dg-do-what-default compile
     }
-} elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+} elseif { [istarget "mips*-*-*"] && [check_effective_target_nomips16] } {
+    if { [check_effective_target_mpaired_single] } {
+        lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    }
     set dg-do-what-default run
 } elseif [istarget "sparc*-*-*"] {
     lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"

[-- Attachment #5: target-supports.patch --]
[-- Type: text/x-diff, Size: 2095 bytes --]

Index: testsuite/lib/target-supports.exp
===================================================================
--- testsuite/lib/target-supports.exp	(revision 161865)
+++ testsuite/lib/target-supports.exp	(working copy)
@@ -1493,7 +1493,8 @@ proc check_effective_target_vect_int { }
 	      || [istarget sparc*-*-*]
 	      || [istarget alpha*-*-*]
 	      || [istarget ia64-*-*] 
-	      || [check_effective_target_arm32] } {
+	      || [check_effective_target_arm32]
+              || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_int_saved 1
 	}
     }
@@ -2029,7 +2030,8 @@ proc check_effective_target_vect_shift {
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
-	     || [check_effective_target_arm32] } {
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_shift_saved 1
 	}
     }
@@ -2143,7 +2145,8 @@ proc check_effective_target_vect_no_int_
 	set et_vect_no_int_max_saved 0
 	if { [istarget sparc*-*-*]
 	     || [istarget spu-*-*]
-	     || [istarget alpha*-*-*] } {
+	     || [istarget alpha*-*-*]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_int_max_saved 1
 	}
     }
@@ -2516,7 +2519,8 @@ proc check_effective_target_vect_no_alig
 	if { [istarget mipsisa64*-*-*]
 	     || [istarget sparc*-*-*]
 	     || [istarget ia64-*-*]
-	     || [check_effective_target_arm32] } { 
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_align_saved 1
 	}
     }
@@ -2707,7 +2711,8 @@ proc check_effective_target_vect_short_m
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
              || [istarget powerpc*-*-*]
-             || [check_effective_target_arm32] } {
+             || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_short_mult_saved 1
 	}
     }

[-- Attachment #6: loongson.patch --]
[-- Type: text/x-diff, Size: 1797 bytes --]

Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 161865)
+++ config/mips/loongson.md	(working copy)
@@ -352,6 +352,16 @@
   "pmulh<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
 
+;; Standard pattern mulm3
+(define_expand "mul<mode>3"
+  [(set (match_operand:VH 0 "register_operand" "=f")
+        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
+                    (match_operand:VH 2 "register_operand" "f")]
+                   UNSPEC_LOONGSON_PMULL))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
+
 ;; Multiply signed integers and store low result.
 (define_insn "loongson_pmull<V_suffix>"
   [(set (match_operand:VH 0 "register_operand" "=f")
@@ -421,6 +431,14 @@
   "psll<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
 
+;; Standard pattern ashrm3
+(define_expand "ashr<mode>3"
+  [(set (match_operand:VWH 0 "register_operand" "=f")
+        (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
+                      (match_operand:SI 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
 ;; Shift right arithmetic.
 (define_insn "loongson_psra<V_suffix>"
   [(set (match_operand:VWH 0 "register_operand" "=f")
@@ -430,6 +448,14 @@
   "psra<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fdiv")])
 
+;; Standard pattern lshrm3
+(define_expand "lshr<mode>3"
+  [(set (match_operand:VWH 0 "register_operand" "=f")
+        (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
+                      (match_operand:SI 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
 ;; Shift right logical.
 (define_insn "loongson_psrl<V_suffix>"
   [(set (match_operand:VWH 0 "register_operand" "=f")

Re: [vect] Ask for review and approving the patch about vect and loongson

[Richard Guenther]

On Fri, Jul 9, 2010 at 10:39 AM, Eric Fisher <joefoxreal@gmail.com> wrote:
> 2010/7/9 Richard Guenther <richard.guenther@gmail.com>:
>>
>> How about splitting the patch?
>>
>> Richard.
>>
>
> Thanks. I put the patch separately now. And the ChageLogs,

The sourcebuild.texi and the fast-math-vect-reduc-8 patch are ok.

Richard.

> gcc/ChangeLog
>  * sourcebuild.texi: Remove duplicated item vect_int_mult.
>  * loongson.md: Add define_expand for standard names mulm3 (VH),
> ashrm3 (VWH), lshrm3 (VWH) to generate SIMD automatically.
>
> testsuite/ChangeLog
>  * fast-math-vect-reduc-8.c: Move dg-require-effective-target after dg-do.
>  * vect.exp: Go on running the testsuite when the target is mips*
>  * target-supports.exp: Check loongson target in vector specific attributes.
>
>
> Thanks,
> Eric
>

Re: [vect] Ask for review and approving the patch about vect and loongson

[Eric Fisher]

[-- Attachment #1: Type: text/plain, Size: 574 bytes --]

2010/7/9 Richard Guenther <richard.guenther@gmail.com>:
> On Fri, Jul 9, 2010 at 10:39 AM, Eric Fisher <joefoxreal@gmail.com> wrote:
>> 2010/7/9 Richard Guenther <richard.guenther@gmail.com>:
>>>
>>> How about splitting the patch?
>>>
>>> Richard.
>>>
>>
>> Thanks. I put the patch separately now. And the ChageLogs,
>
> The sourcebuild.texi and the fast-math-vect-reduc-8 patch are ok.
>
> Richard.

I would like to rewrite the vect.exp patch as the following
attachment, which looks better than before.

ChangeLog
  * vect.exp: add check for loongson target

Thanks,
Eric

[-- Attachment #2: vect2.patch --]
[-- Type: text/x-diff, Size: 834 bytes --]

Index: testsuite/gcc.dg/vect/vect.exp
===================================================================
--- testsuite/gcc.dg/vect/vect.exp	(revision 161865)
+++ testsuite/gcc.dg/vect/vect.exp	(working copy)
@@ -77,9 +77,12 @@ if  [istarget "powerpc-*paired*"]  {
 	set dg-do-what-default compile
     }
 } elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
+	   && ([check_effective_target_mpaired_single]
+               || [check_effective_target_mips_loongson])
 	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    if { [check_effective_target_mpaired_single] } {
+        lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    }
     set dg-do-what-default run
 } elseif [istarget "sparc*-*-*"] {
     lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"

Re: [vect] Ask for review and approving the patch about vect and loongson

[Richard Sandiford]

The updated vect.patch is OK.

The target-supports.patch is OK if you break the line immediately before
the "&&"; the lines are too long as-is.

As far as loongson.patch goes:

Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 161865)
+++ config/mips/loongson.md	(working copy)
@@ -352,6 +352,16 @@
   "pmulh<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
 
+;; Standard pattern mulm3
+(define_expand "mul<mode>3"
+  [(set (match_operand:VH 0 "register_operand" "=f")
+        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
+                    (match_operand:VH 2 "register_operand" "f")]
+                   UNSPEC_LOONGSON_PMULL))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
+
 ;; Multiply signed integers and store low result.
 (define_insn "loongson_pmull<V_suffix>"
   [(set (match_operand:VH 0 "register_operand" "=f")

Instead rename loongson_pmull<V_suffix> to mul<mode>3 and add #defines
to mips.c to make CODE_FOR_loongson_pmullh an alias for CODE_FOR_mulhi3,
etc.  Grep for CODE_FOR_loongson to see where I mean.

The patch adds patterns for shifts right but not shifts left.  Was that
deliberate?

The same rename-and-#define common would apply to the shifts, but I'm
worried.  The loongson insns are all "infinite precision" shifts
(any V2HI << 16 == 0), whereas MIPS is a SHIFT_COUNT_TRUNCATED
target (implying V2HI << 16 should be an identity operation).
This could in theory cause us to miscompile things like:

   v2hi >> (shift & 15)

and although I can't come up with a testcase, I think the problem
is still there.

Admittedly this means the current code is wrong too.  It should be
using UNSPECs instead of shift rtxes.

One fix would be to make SHIFT_COUNT_TRUNCATED take a mode argument
(and turn it into a target hook at the same time).

Richard

Re: [vect] Ask for review and approving the patch about vect and loongson

[Eric Fisher]

[-- Attachment #1: Type: text/plain, Size: 2451 bytes --]

2010/7/10 Richard Sandiford <rdsandiford@googlemail.com>:
> The updated vect.patch is OK.
>
> The target-supports.patch is OK if you break the line immediately before
> the "&&"; the lines are too long as-is.

OK, I've updated the patch in the attachment.

> As far as loongson.patch goes:
>
> Index: config/mips/loongson.md
> ===================================================================
> --- config/mips/loongson.md     (revision 161865)
> +++ config/mips/loongson.md     (working copy)
> @@ -352,6 +352,16 @@
>   "pmulh<V_suffix>\t%0,%1,%2"
>   [(set_attr "type" "fmul")])
>
> +;; Standard pattern mulm3
> +(define_expand "mul<mode>3"
> +  [(set (match_operand:VH 0 "register_operand" "=f")
> +        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
> +                    (match_operand:VH 2 "register_operand" "f")]
> +                   UNSPEC_LOONGSON_PMULL))]
> +  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
> +  "")
> +
> +
>  ;; Multiply signed integers and store low result.
>  (define_insn "loongson_pmull<V_suffix>"
>   [(set (match_operand:VH 0 "register_operand" "=f")
>
> Instead rename loongson_pmull<V_suffix> to mul<mode>3 and add #defines
> to mips.c to make CODE_FOR_loongson_pmullh an alias for CODE_FOR_mulhi3,
> etc.  Grep for CODE_FOR_loongson to see where I mean.

Thanks for the helpful information. I've changed the patch in the attachment.

> The patch adds patterns for shifts right but not shifts left.  Was that
> deliberate?

Oh, I missed it. Now I've added it.

> The same rename-and-#define common would apply to the shifts, but I'm
> worried.  The loongson insns are all "infinite precision" shifts
> (any V2HI << 16 == 0), whereas MIPS is a SHIFT_COUNT_TRUNCATED
> target (implying V2HI << 16 should be an identity operation).
> This could in theory cause us to miscompile things like:
>
>   v2hi >> (shift & 15)
>
> and although I can't come up with a testcase, I think the problem
> is still there.
>
> Admittedly this means the current code is wrong too.  It should be
> using UNSPECs instead of shift rtxes.
>
> One fix would be to make SHIFT_COUNT_TRUNCATED take a mode argument
> (and turn it into a target hook at the same time).
>
> Richard
>

I'm going to take a look at this problem. Do you think that it is all
right to first submit the current patch and leave this problem in the
next one separately?

Thanks
Eric

[-- Attachment #2: target-supports.patch --]
[-- Type: text/x-diff, Size: 2191 bytes --]

Index: testsuite/lib/target-supports.exp
===================================================================
--- testsuite/lib/target-supports.exp	(revision 162065)
+++ testsuite/lib/target-supports.exp	(working copy)
@@ -1493,7 +1493,9 @@ proc check_effective_target_vect_int { }
 	      || [istarget sparc*-*-*]
 	      || [istarget alpha*-*-*]
 	      || [istarget ia64-*-*] 
-	      || [check_effective_target_arm32] } {
+	      || [check_effective_target_arm32]
+              || ([istarget mips*-*-*]
+                   && [check_effective_target_mips_loongson]) } {
 	   set et_vect_int_saved 1
 	}
     }
@@ -2029,7 +2031,9 @@ proc check_effective_target_vect_shift {
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
-	     || [check_effective_target_arm32] } {
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*]
+                  && [check_effective_target_mips_loongson]) } {
 	   set et_vect_shift_saved 1
 	}
     }
@@ -2143,7 +2147,9 @@ proc check_effective_target_vect_no_int_
 	set et_vect_no_int_max_saved 0
 	if { [istarget sparc*-*-*]
 	     || [istarget spu-*-*]
-	     || [istarget alpha*-*-*] } {
+	     || [istarget alpha*-*-*]
+             || ([istarget mips*-*-*]
+                  && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_int_max_saved 1
 	}
     }
@@ -2516,7 +2522,9 @@ proc check_effective_target_vect_no_alig
 	if { [istarget mipsisa64*-*-*]
 	     || [istarget sparc*-*-*]
 	     || [istarget ia64-*-*]
-	     || [check_effective_target_arm32] } { 
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*]
+                  && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_align_saved 1
 	}
     }
@@ -2707,7 +2715,9 @@ proc check_effective_target_vect_short_m
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
              || [istarget powerpc*-*-*]
-             || [check_effective_target_arm32] } {
+             || [check_effective_target_arm32]
+             || ([istarget mips*-*-*]
+                  && [check_effective_target_mips_loongson]) } {
 	   set et_vect_short_mult_saved 1
 	}
     }

[-- Attachment #3: loongson.patch --]
[-- Type: text/x-diff, Size: 2438 bytes --]

Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 162065)
+++ config/mips/loongson.md	(working copy)
@@ -353,7 +353,7 @@
   [(set_attr "type" "fmul")])
 
 ;; Multiply signed integers and store low result.
-(define_insn "loongson_pmull<V_suffix>"
+(define_insn "mul<mode>3"
   [(set (match_operand:VH 0 "register_operand" "=f")
         (unspec:VH [(match_operand:VH 1 "register_operand" "f")
 		    (match_operand:VH 2 "register_operand" "f")]
@@ -413,7 +413,7 @@
   [(set_attr "type" "fmul")])
 
 ;; Shift left logical.
-(define_insn "loongson_psll<V_suffix>"
+(define_insn "ashl<mode>3"
   [(set (match_operand:VWH 0 "register_operand" "=f")
         (ashift:VWH (match_operand:VWH 1 "register_operand" "f")
 		    (match_operand:SI 2 "register_operand" "f")))]
@@ -422,7 +422,7 @@
   [(set_attr "type" "fmul")])
 
 ;; Shift right arithmetic.
-(define_insn "loongson_psra<V_suffix>"
+(define_insn "ashr<mode>3"
   [(set (match_operand:VWH 0 "register_operand" "=f")
         (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
 		      (match_operand:SI 2 "register_operand" "f")))]
@@ -431,7 +431,7 @@
   [(set_attr "type" "fdiv")])
 
 ;; Shift right logical.
-(define_insn "loongson_psrl<V_suffix>"
+(define_insn "lshr<mode>3"
   [(set (match_operand:VWH 0 "register_operand" "=f")
         (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
 		      (match_operand:SI 2 "register_operand" "f")))]
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c	(revision 162065)
+++ config/mips/mips.c	(working copy)
@@ -12667,6 +12667,13 @@ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BU
 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
+#define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
+#define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
+#define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
+#define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
+#define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
+#define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
+#define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3

Re: [vect] Ask for review and approving the patch about vect and loongson

[Richard Sandiford]

Eric Fisher <joefoxreal@gmail.com> writes:
> 2010/7/10 Richard Sandiford <rdsandiford@googlemail.com>:
>> The updated vect.patch is OK.
>>
>> The target-supports.patch is OK if you break the line immediately before
>> the "&&"; the lines are too long as-is.
>
> OK, I've updated the patch in the attachment.

Looks good.  OK to apply.

>> As far as loongson.patch goes:
>>
>> Index: config/mips/loongson.md
>> ===================================================================
>> --- config/mips/loongson.md     (revision 161865)
>> +++ config/mips/loongson.md     (working copy)
>> @@ -352,6 +352,16 @@
>>   "pmulh<V_suffix>\t%0,%1,%2"
>>   [(set_attr "type" "fmul")])
>>
>> +;; Standard pattern mulm3
>> +(define_expand "mul<mode>3"
>> +  [(set (match_operand:VH 0 "register_operand" "=f")
>> +        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
>> +                    (match_operand:VH 2 "register_operand" "f")]
>> +                   UNSPEC_LOONGSON_PMULL))]
>> +  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
>> +  "")
>> +
>> +
>>  ;; Multiply signed integers and store low result.
>>  (define_insn "loongson_pmull<V_suffix>"
>>   [(set (match_operand:VH 0 "register_operand" "=f")
>>
>> Instead rename loongson_pmull<V_suffix> to mul<mode>3 and add #defines
>> to mips.c to make CODE_FOR_loongson_pmullh an alias for CODE_FOR_mulhi3,
>> etc.  Grep for CODE_FOR_loongson to see where I mean.
>
> Thanks for the helpful information. I've changed the patch in the attachment.

Sorry, I forgot to ask you to change the pattern from an UNSPEC to
a MULT at the same time.  The multiplication part is OK with that fixed.

>> The same rename-and-#define common would apply to the shifts, but I'm
>> worried.  The loongson insns are all "infinite precision" shifts
>> (any V2HI << 16 == 0), whereas MIPS is a SHIFT_COUNT_TRUNCATED
>> target (implying V2HI << 16 should be an identity operation).
>> This could in theory cause us to miscompile things like:
>>
>>   v2hi >> (shift & 15)
>>
>> and although I can't come up with a testcase, I think the problem
>> is still there.
>>
>> Admittedly this means the current code is wrong too.  It should be
>> using UNSPECs instead of shift rtxes.
>>
>> One fix would be to make SHIFT_COUNT_TRUNCATED take a mode argument
>> (and turn it into a target hook at the same time).
>>
>> Richard
>
> I'm going to take a look at this problem. Do you think that it is all
> right to first submit the current patch and leave this problem in the
> next one separately?

No, I'm afraid the truncation needs to be sorted out before the shift
changes go in.  As things stand, the shift changes would in principle
introduce a wrong-code regression.

Richard

Re: [vect] Ask for review and approving the patch about vect and loongson

[Eric Fisher]

[-- Attachment #1: Type: text/plain, Size: 1571 bytes --]

2010/7/13 Richard Sandiford <rdsandiford@googlemail.com>:
>>> As far as loongson.patch goes:
>>>
>>> Index: config/mips/loongson.md
>>> ===================================================================
>>> --- config/mips/loongson.md     (revision 161865)
>>> +++ config/mips/loongson.md     (working copy)
>>> @@ -352,6 +352,16 @@
>>>   "pmulh<V_suffix>\t%0,%1,%2"
>>>   [(set_attr "type" "fmul")])
>>>
>>> +;; Standard pattern mulm3
>>> +(define_expand "mul<mode>3"
>>> +  [(set (match_operand:VH 0 "register_operand" "=f")
>>> +        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
>>> +                    (match_operand:VH 2 "register_operand" "f")]
>>> +                   UNSPEC_LOONGSON_PMULL))]
>>> +  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
>>> +  "")
>>> +
>>> +
>>>  ;; Multiply signed integers and store low result.
>>>  (define_insn "loongson_pmull<V_suffix>"
>>>   [(set (match_operand:VH 0 "register_operand" "=f")
>>>
>>> Instead rename loongson_pmull<V_suffix> to mul<mode>3 and add #defines
>>> to mips.c to make CODE_FOR_loongson_pmullh an alias for CODE_FOR_mulhi3,
>>> etc.  Grep for CODE_FOR_loongson to see where I mean.
>>
>> Thanks for the helpful information. I've changed the patch in the attachment.
>
> Sorry, I forgot to ask you to change the pattern from an UNSPEC to
> a MULT at the same time.  The multiplication part is OK with that fixed.

Thanks. I've updated the patch in the attachment.

BTW, I still don't have svn write access and copyright assignment. :(

Regards,
Eric

[-- Attachment #2: loongson_mult.patch --]
[-- Type: text/x-diff, Size: 1611 bytes --]

Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 162065)
+++ config/mips/loongson.md	(working copy)
@@ -31,7 +31,6 @@
   UNSPEC_LOONGSON_PMOVMSK
   UNSPEC_LOONGSON_PMULHU
   UNSPEC_LOONGSON_PMULH
-  UNSPEC_LOONGSON_PMULL
   UNSPEC_LOONGSON_PMULU
   UNSPEC_LOONGSON_PASUBUB
   UNSPEC_LOONGSON_BIADD
@@ -353,11 +352,10 @@
   [(set_attr "type" "fmul")])
 
 ;; Multiply signed integers and store low result.
-(define_insn "loongson_pmull<V_suffix>"
+(define_insn "mul<mode>3"
   [(set (match_operand:VH 0 "register_operand" "=f")
-        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
-		    (match_operand:VH 2 "register_operand" "f")]
-		   UNSPEC_LOONGSON_PMULL))]
+        (mult:VH (match_operand:VH 1 "register_operand" "f")
+		    (match_operand:VH 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "pmull<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c	(revision 162065)
+++ config/mips/mips.c	(working copy)
@@ -12667,6 +12667,7 @@ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BU
 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
+#define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3

Re: [vect] Ask for review and approving the patch about vect and loongson

[Richard Sandiford]

Eric Fisher <joefoxreal@gmail.com> writes:
> Thanks. I've updated the patch in the attachment.

Watch the formatting: the (match_operand: ...)s should line up vertically.

The patch is OK with that change.  Obviously we'll have to wait until
the copyright assignment is sorted out before the patches can be applied.

Richard

Re: [vect] Ask for review and approving the patch about vect and loongson

[Eric Fisher]

[-- Attachment #1: Type: text/plain, Size: 660 bytes --]

2010/7/14 Richard Sandiford <rdsandiford@googlemail.com>:

> Watch the formatting: the (match_operand: ...)s should line up vertically.

Thanks. I've updated the patch.

> This could in theory cause us to miscompile things like:
>
>   v2hi >> (shift & 15)
>
> and although I can't come up with a testcase, I think the problem
> is still there.
>
> Admittedly this means the current code is wrong too.  It should be
> using UNSPECs instead of shift rtxes.
>
> One fix would be to make SHIFT_COUNT_TRUNCATED take a mode argument
> (and turn it into a target hook at the same time).
>

Richard, you're right. I can produce this problem with a testcase now.

Eric

[-- Attachment #2: loongson_mult.patch --]
[-- Type: text/x-diff, Size: 1001 bytes --]

Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 162124)
+++ config/mips/loongson.md	(working copy)
@@ -31,7 +31,6 @@
   UNSPEC_LOONGSON_PMOVMSK
   UNSPEC_LOONGSON_PMULHU
   UNSPEC_LOONGSON_PMULH
-  UNSPEC_LOONGSON_PMULL
   UNSPEC_LOONGSON_PMULU
   UNSPEC_LOONGSON_PASUBUB
   UNSPEC_LOONGSON_BIADD
@@ -353,11 +352,10 @@
   [(set_attr "type" "fmul")])
 
 ;; Multiply signed integers and store low result.
-(define_insn "loongson_pmull<V_suffix>"
+(define_insn "mul<mode>3"
   [(set (match_operand:VH 0 "register_operand" "=f")
-        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
-		    (match_operand:VH 2 "register_operand" "f")]
-		   UNSPEC_LOONGSON_PMULL))]
+        (mult:VH (match_operand:VH 1 "register_operand" "f")
+                 (match_operand:VH 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "pmull<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])

Re: [vect] Ask for review and approving the patch about vect and loongson

[Mingjie Xing]

[-- Attachment #1: Type: text/plain, Size: 2103 bytes --]

2010/8/24 Richard Sandiford <rdsandiford@googlemail.com>:
> Richard Guenther <richard.guenther@gmail.com> writes:
>> On Sat, Aug 21, 2010 at 10:29 AM, Richard Sandiford
>> <rdsandiford@googlemail.com> wrote:
>>> Uros Bizjak <ubizjak@gmail.com> writes:
>>>> On Tue, Aug 17, 2010 at 11:49 AM, Mingjie Xing <mingjie.xing@gmail.com> wrote:
>>>>> Updated. See the attachment.
>>>>
>>>> Perhaps we should extend the comment a bit:
>>>>
>>>> +# Check whether the vectorizer tests are supported by the target and append
>>>> +# additional target-dependent compile flags to DEFAULT_VECTFLAGS.  Also
>>>> +# set dg-do-what-default to either compile or run, depending on target
>>>> +# capabilities.  Return 1 if vectorizer tests are supported by
>>>> target, 0 otherwise.
>>>>
>>>>> Is it OK?
>>>>
>>>> Looks OK to me.  Richi, can you please formally approve the patch?
>>>
>>> Seems like this might have got stuck.  Mingjie's original patch is
>>> certainly a step forward in its own right, so Mingjie, please feel free
>>> to commit your original MIPS-specific gcc.dg/vect/vect.exp patch if you
>>> don't get an approval for this one in the next couple of days.  Please
>>> update the other two vect.exps in the same way, at the same time.
>>
>> As we do not have an (active) testsuite maintainer right now please treat
>> target specific changes as covered by your target maintainership.
>
> TBH, I'd been doing that even before Janis left. ;-)  And that's why
> I'd approved Mingjie's original patch when he posted it, before Uros
> pointed out that there were two other copies to update.
>
> I wasn't sure the patch to unify the three copies qualified as a
> MIPS-specific change though.  It changes the behaviour for ARM.
>
> Richard
>

Hi all, to make this easier, I now just modify the MIPS-specific
parts. The patch has been checked in. Thanks again.

Mingjie

2010-08-24  Mingjie Xing  <mingjie.xing@gmail.com>

        * gcc.dg/vect/vect.exp: Check loongson targets
        * g++.dg/vect/vect.exp: Likewise
        * gfortran.dg/vect/vect.exp: Likewise

[-- Attachment #2: vect.patch --]
[-- Type: text/x-diff, Size: 2367 bytes --]

Index: gcc.dg/vect/vect.exp
===================================================================
--- gcc.dg/vect/vect.exp	(revision 163494)
+++ gcc.dg/vect/vect.exp	(working copy)
@@ -74,9 +74,12 @@ if  [istarget "powerpc-*paired*"]  {
 	set dg-do-what-default compile
     }
 } elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
+	   && ([check_effective_target_mpaired_single]
+		|| [check_effective_target_mips_loongson])
 	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    if { [check_effective_target_mpaired_single] } {
+	lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    }
     set dg-do-what-default run
 } elseif [istarget "sparc*-*-*"] {
     lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
Index: g++.dg/vect/vect.exp
===================================================================
--- g++.dg/vect/vect.exp	(revision 163494)
+++ g++.dg/vect/vect.exp	(working copy)
@@ -82,9 +82,12 @@ if  [istarget "powerpc-*paired*"]  {
 	set dg-do-what-default compile
     }
 } elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
+	   && ([check_effective_target_mpaired_single]
+		|| [check_effective_target_mips_loongson])
 	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    if { [check_effective_target_mpaired_single] } {
+	lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    }
     set dg-do-what-default run
 } elseif [istarget "sparc*-*-*"] {
     lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
Index: gfortran.dg/vect/vect.exp
===================================================================
--- gfortran.dg/vect/vect.exp	(revision 163494)
+++ gfortran.dg/vect/vect.exp	(working copy)
@@ -75,9 +75,12 @@ if  [istarget "powerpc-*paired*"]  {
 	set dg-do-what-default compile
     }
 } elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
+	   && ([check_effective_target_mpaired_single]
+		|| [check_effective_target_mips_loongson])
 	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    if { [check_effective_target_mpaired_single] } {
+	lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    }
     set dg-do-what-default run
 } elseif [istarget "sparc*-*-*"] {
     lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"

Re: [vect] Ask for review and approving the patch about vect and loongson

[Richard Sandiford]

Richard Guenther <richard.guenther@gmail.com> writes:
> On Sat, Aug 21, 2010 at 10:29 AM, Richard Sandiford
> <rdsandiford@googlemail.com> wrote:
>> Uros Bizjak <ubizjak@gmail.com> writes:
>>> On Tue, Aug 17, 2010 at 11:49 AM, Mingjie Xing <mingjie.xing@gmail.com> wrote:
>>>> Updated. See the attachment.
>>>
>>> Perhaps we should extend the comment a bit:
>>>
>>> +# Check whether the vectorizer tests are supported by the target and append
>>> +# additional target-dependent compile flags to DEFAULT_VECTFLAGS.  Also
>>> +# set dg-do-what-default to either compile or run, depending on target
>>> +# capabilities.  Return 1 if vectorizer tests are supported by
>>> target, 0 otherwise.
>>>
>>>> Is it OK?
>>>
>>> Looks OK to me.  Richi, can you please formally approve the patch?
>>
>> Seems like this might have got stuck.  Mingjie's original patch is
>> certainly a step forward in its own right, so Mingjie, please feel free
>> to commit your original MIPS-specific gcc.dg/vect/vect.exp patch if you
>> don't get an approval for this one in the next couple of days.  Please
>> update the other two vect.exps in the same way, at the same time.
>
> As we do not have an (active) testsuite maintainer right now please treat
> target specific changes as covered by your target maintainership.

TBH, I'd been doing that even before Janis left. ;-)  And that's why
I'd approved Mingjie's original patch when he posted it, before Uros
pointed out that there were two other copies to update.

I wasn't sure the patch to unify the three copies qualified as a
MIPS-specific change though.  It changes the behaviour for ARM.

Richard

Re: [vect] Ask for review and approving the patch about vect and loongson

[Richard Guenther]

On Sat, Aug 21, 2010 at 10:29 AM, Richard Sandiford
<rdsandiford@googlemail.com> wrote:
> Uros Bizjak <ubizjak@gmail.com> writes:
>> On Tue, Aug 17, 2010 at 11:49 AM, Mingjie Xing <mingjie.xing@gmail.com> wrote:
>>> Updated. See the attachment.
>>
>> Perhaps we should extend the comment a bit:
>>
>> +# Check whether the vectorizer tests are supported by the target and append
>> +# additional target-dependent compile flags to DEFAULT_VECTFLAGS.  Also
>> +# set dg-do-what-default to either compile or run, depending on target
>> +# capabilities.  Return 1 if vectorizer tests are supported by
>> target, 0 otherwise.
>>
>>> Is it OK?
>>
>> Looks OK to me.  Richi, can you please formally approve the patch?
>
> Seems like this might have got stuck.  Mingjie's original patch is
> certainly a step forward in its own right, so Mingjie, please feel free
> to commit your original MIPS-specific gcc.dg/vect/vect.exp patch if you
> don't get an approval for this one in the next couple of days.  Please
> update the other two vect.exps in the same way, at the same time.

As we do not have an (active) testsuite maintainer right now please treat
target specific changes as covered by your target maintainership.

Richard.

> Richard
>

Re: [vect] Ask for review and approving the patch about vect and loongson

[Richard Sandiford]

Uros Bizjak <ubizjak@gmail.com> writes:
> On Tue, Aug 17, 2010 at 11:49 AM, Mingjie Xing <mingjie.xing@gmail.com> wrote:
>> Updated. See the attachment.
>
> Perhaps we should extend the comment a bit:
>
> +# Check whether the vectorizer tests are supported by the target and append
> +# additional target-dependent compile flags to DEFAULT_VECTFLAGS.  Also
> +# set dg-do-what-default to either compile or run, depending on target
> +# capabilities.  Return 1 if vectorizer tests are supported by
> target, 0 otherwise.
>
>> Is it OK?
>
> Looks OK to me.  Richi, can you please formally approve the patch?

Seems like this might have got stuck.  Mingjie's original patch is
certainly a step forward in its own right, so Mingjie, please feel free
to commit your original MIPS-specific gcc.dg/vect/vect.exp patch if you
don't get an approval for this one in the next couple of days.  Please
update the other two vect.exps in the same way, at the same time.

Richard

Re: [vect] Ask for review and approving the patch about vect and loongson

[Mingjie Xing]

2010/8/17 Uros Bizjak <ubizjak@gmail.com>:
>
> Looks OK to me.  Richi, can you please formally approve the patch?
>
> Thanks,
> Uros.
>

Ping

Re: [vect] Ask for review and approving the patch about vect and loongson

[Uros Bizjak]

On Tue, Aug 17, 2010 at 11:49 AM, Mingjie Xing <mingjie.xing@gmail.com> wrote:
> 2010/8/17 Uros Bizjak <ubizjak@gmail.com>:
>> On Tue, Aug 17, 2010 at 8:37 AM, Mingjie Xing <mingjie.xing@gmail.com> wrote:
>> The difference is not intentional, it looks that someone changed only
>> gcc.dg/vect/vect.exp. So, in case of doubt, simply copy the
>> functionality from gcc.dg/vect, this should be the master copy for
>> your function.
>
> All right. The current function is based on gcc.dg/vect/vect.exp.
>
>> +# Check whether the vect tests are supported by the target and set additional
>> +# target-dependent vector flags, which can be overriden by using dg-options
>> +# in individual tests. Return 1 if the target supports, 0 otherwise.
>>
>> ... whether the vectorizer tests are supported ... Return 1 if
>> vectorizer tests are supported by target, 0 otherwise.
>
> Updated. See the attachment.

Perhaps we should extend the comment a bit:

+# Check whether the vectorizer tests are supported by the target and append
+# additional target-dependent compile flags to DEFAULT_VECTFLAGS.  Also
+# set dg-do-what-default to either compile or run, depending on target
+# capabilities.  Return 1 if vectorizer tests are supported by
target, 0 otherwise.

> Is it OK?

Looks OK to me.  Richi, can you please formally approve the patch?

Thanks,
Uros.

Re: [vect] Ask for review and approving the patch about vect and loongson

[Mingjie Xing]

[-- Attachment #1: Type: text/plain, Size: 846 bytes --]

2010/8/17 Uros Bizjak <ubizjak@gmail.com>:
> On Tue, Aug 17, 2010 at 8:37 AM, Mingjie Xing <mingjie.xing@gmail.com> wrote:
> The difference is not intentional, it looks that someone changed only
> gcc.dg/vect/vect.exp. So, in case of doubt, simply copy the
> functionality from gcc.dg/vect, this should be the master copy for
> your function.

All right. The current function is based on gcc.dg/vect/vect.exp.

> +# Check whether the vect tests are supported by the target and set additional
> +# target-dependent vector flags, which can be overriden by using dg-options
> +# in individual tests. Return 1 if the target supports, 0 otherwise.
>
> ... whether the vectorizer tests are supported ... Return 1 if
> vectorizer tests are supported by target, 0 otherwise.

Updated. See the attachment.

> Thanks,
> Uros.
>

Is it OK?

Thanks,
Mingjie

[-- Attachment #2: vect.patch --]
[-- Type: text/x-diff, Size: 12472 bytes --]

Index: gcc.dg/vect/vect.exp
===================================================================
--- gcc.dg/vect/vect.exp	(revision 163291)
+++ gcc.dg/vect/vect.exp	(working copy)
@@ -37,81 +37,7 @@ set save-dg-do-what-default ${dg-do-what
 # Skip these tests for targets that do not support generating vector
 # code.  Set additional target-dependent vector flags, which can be
 # overridden by using dg-options in individual tests.
-if  [istarget "powerpc-*paired*"]  {
-   lappend DEFAULT_VECTCFLAGS "-mpaired"
-    if [check_750cl_hw_available] {
-        set dg-do-what-default run 
-    } else {
-        set dg-do-what-default compile
-    }
-} elseif [istarget "powerpc*-*-*"] {
-    # Skip targets not supporting -maltivec.
-    if ![is-effective-target powerpc_altivec_ok] {
-	return
-    }
-
-    lappend DEFAULT_VECTCFLAGS "-maltivec"
-    if [check_vsx_hw_available]  {
-      lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
-    }
-
-    if [check_vmx_hw_available] {
-	set dg-do-what-default run
-    } else {
-	if [is-effective-target ilp32] {
-	    # Specify a cpu that supports VMX for compile-only tests.
-	    lappend DEFAULT_VECTCFLAGS "-mcpu=970"
-	}
-	set dg-do-what-default compile
-    }
-} elseif { [istarget  "spu-*-*"] } {
-   set dg-do-what-default run
-} elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
-    lappend DEFAULT_VECTCFLAGS "-msse2"
-    if { [check_effective_target_sse2_runtime] } {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
-    set dg-do-what-default run
-} elseif [istarget "sparc*-*-*"] {
-    lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
-    if [check_effective_target_ultrasparc_hw] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "alpha*-*-*"] {
-    # Alpha's vectorization capabilities are extremely limited.
-    # It's more effort than its worth disabling all of the tests
-    # that it cannot pass.  But if you actually want to see what
-    # does work, command out the return.
-    return
-
-    lappend DEFAULT_VECTCFLAGS "-mmax"
-    if [check_alpha_max_hw_available] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "ia64-*-*"] {
-    set dg-do-what-default run
-} elseif [is-effective-target arm_neon_ok] {
-    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
-    # NEON does not support denormals, so is not used for vectorization by
-    # default to avoid loss of precision.  We must pass -ffast-math to test
-    # vectorization of float operations.
-    lappend DEFAULT_VECTCFLAGS "-ffast-math"
-    if [is-effective-target arm_neon_hw] {
-      set dg-do-what-default run
-    } else {
-      set dg-do-what-default compile
-    }
-} else {
+if ![check_vect_support_and_set_flags] {
     return
 }
 
Index: g++.dg/vect/vect.exp
===================================================================
--- g++.dg/vect/vect.exp	(revision 163291)
+++ g++.dg/vect/vect.exp	(working copy)
@@ -45,77 +45,7 @@ lappend DEFAULT_VECTCFLAGS "-O2" "-ftree
 # Skip these tests for targets that do not support generating vector
 # code.  Set additional target-dependent vector flags, which can be
 # overridden by using dg-options in individual tests.
-if  [istarget "powerpc-*paired*"]  {
-   lappend DEFAULT_VECTCFLAGS "-mpaired"
-    if [check_750cl_hw_available] {
-        set dg-do-what-default run 
-    } else {
-        set dg-do-what-default compile
-    }
-} elseif [istarget "powerpc*-*-*"] {
-    # Skip targets not supporting -maltivec.
-    if ![is-effective-target powerpc_altivec_ok] {
-	return
-    }
-
-    lappend DEFAULT_VECTCFLAGS "-maltivec"
-    if [check_vsx_hw_available]  {
-      lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
-    }
-
-    if [check_vmx_hw_available] {
-	set dg-do-what-default run
-    } else {
-	if [is-effective-target ilp32] {
-	    # Specify a cpu that supports VMX for compile-only tests.
-	    lappend DEFAULT_VECTCFLAGS "-mcpu=970"
-	}
-	set dg-do-what-default compile
-    }
-} elseif { [istarget  "spu-*-*"] } {
-   set dg-do-what-default run
-} elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
-    lappend DEFAULT_VECTCFLAGS "-msse2"
-    if { [check_effective_target_sse2_runtime] } {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
-    set dg-do-what-default run
-} elseif [istarget "sparc*-*-*"] {
-    lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
-    if [check_effective_target_ultrasparc_hw] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "alpha*-*-*"] {
-    # Alpha's vectorization capabilities are extremely limited.
-    # It's more effort than its worth disabling all of the tests
-    # that it cannot pass.  But if you actually want to see what
-    # does work, command out the return.
-    return
-
-    lappend DEFAULT_VECTCFLAGS "-mmax"
-    if [check_alpha_max_hw_available] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "ia64-*-*"] {
-    set dg-do-what-default run
-} elseif [is-effective-target arm_neon_ok] {
-    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
-    if [is-effective-target arm_neon_hw] {
-      set dg-do-what-default run
-    } else {
-      set dg-do-what-default compile
-    }
-} else {
+if ![check_vect_support_and_set_flags] {
     return
 }
 
Index: lib/target-supports.exp
===================================================================
--- lib/target-supports.exp	(revision 163291)
+++ lib/target-supports.exp	(working copy)
@@ -3547,3 +3547,97 @@ proc check_effective_target_c++ { } {
     }
  return 0
 }
+
+# Check whether the vectorizer tests are supported by the target and set
+# additional target-dependent vector flags, which can be overriden by using
+# dg-options in individual tests. Return 1 if vectorizer tests are supported
+# by target, 0 otherwise.
+
+proc check_vect_support_and_set_flags { } {
+    global DEFAULT_VECTCFLAGS
+    global dg-do-what-default
+
+    if  [istarget "powerpc-*paired*"]  {
+        lappend DEFAULT_VECTCFLAGS "-mpaired"
+        if [check_750cl_hw_available] {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } elseif [istarget "powerpc*-*-*"] {
+        # Skip targets not supporting -maltivec.
+        if ![is-effective-target powerpc_altivec_ok] {
+            return 0
+        }
+
+        lappend DEFAULT_VECTCFLAGS "-maltivec"
+        if [check_vsx_hw_available]  {
+            lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
+        }
+
+        if [check_vmx_hw_available] {
+            set dg-do-what-default run
+        } else {
+            if [is-effective-target ilp32] {
+                # Specify a cpu that supports VMX for compile-only tests.
+                lappend DEFAULT_VECTCFLAGS "-mcpu=970"
+            }
+            set dg-do-what-default compile
+        }
+    } elseif { [istarget  "spu-*-*"] } {
+        set dg-do-what-default run
+    } elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
+        lappend DEFAULT_VECTCFLAGS "-msse2"
+        if { [check_effective_target_sse2_runtime] } {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } elseif { [istarget "mips*-*-*"]
+               && ([check_effective_target_mpaired_single]
+                    || [check_effective_target_mips_loongson])
+               && [check_effective_target_nomips16] } {
+        if { [check_effective_target_mpaired_single] } {
+            lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+        }
+        set dg-do-what-default run
+    } elseif [istarget "sparc*-*-*"] {
+        lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
+        if [check_effective_target_ultrasparc_hw] {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } elseif [istarget "alpha*-*-*"] {
+        # Alpha's vectorization capabilities are extremely limited.
+        # It's more effort than its worth disabling all of the tests
+        # that it cannot pass.  But if you actually want to see what
+        # does work, command out the return.
+        return 0
+
+        lappend DEFAULT_VECTCFLAGS "-mmax"
+        if [check_alpha_max_hw_available] {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } elseif [istarget "ia64-*-*"] {
+        set dg-do-what-default run
+    } elseif [is-effective-target arm_neon_ok] {
+        eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
+        # NEON does not support denormals, so is not used for vectorization by
+        # default to avoid loss of precision.  We must pass -ffast-math to test
+        # vectorization of float operations.
+        lappend DEFAULT_VECTCFLAGS "-ffast-math"
+        if [is-effective-target arm_neon_hw] {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } else {
+        return 0
+    }
+
+    return 1
+}
+
Index: gfortran.dg/vect/vect.exp
===================================================================
--- gfortran.dg/vect/vect.exp	(revision 163291)
+++ gfortran.dg/vect/vect.exp	(working copy)
@@ -38,77 +38,7 @@ set save-dg-do-what-default ${dg-do-what
 # Skip these tests for targets that do not support generating vector
 # code.  Set additional target-dependent vector flags, which can be
 # overridden by using dg-options in individual tests.
-if  [istarget "powerpc-*paired*"]  {
-   lappend DEFAULT_VECTCFLAGS "-mpaired"
-    if [check_750cl_hw_available] {
-        set dg-do-what-default run 
-    } else {
-        set dg-do-what-default compile
-    }
-} elseif [istarget "powerpc*-*-*"] {
-    # Skip targets not supporting -maltivec.
-    if ![is-effective-target powerpc_altivec_ok] {
-	return
-    }
-
-    lappend DEFAULT_VECTCFLAGS "-maltivec"
-    if [check_vsx_hw_available]  {
-      lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
-    }
-
-    if [check_vmx_hw_available] {
-	set dg-do-what-default run
-    } else {
-	if [is-effective-target ilp32] {
-	    # Specify a cpu that supports VMX for compile-only tests.
-	    lappend DEFAULT_VECTCFLAGS "-mcpu=970"
-	}
-	set dg-do-what-default compile
-    }
-} elseif { [istarget  "spu-*-*"] } {
-   set dg-do-what-default run
-} elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
-    lappend DEFAULT_VECTCFLAGS "-msse2"
-    if { [check_effective_target_sse2_runtime] } {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
-    set dg-do-what-default run
-} elseif [istarget "sparc*-*-*"] {
-    lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
-    if [check_effective_target_ultrasparc_hw] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "alpha*-*-*"] {
-    # Alpha's vectorization capabilities are extremely limited.
-    # It's more effort than its worth disabling all of the tests
-    # that it cannot pass.  But if you actually want to see what
-    # does work, command out the return.
-    return
-
-    lappend DEFAULT_VECTCFLAGS "-mmax"
-    if [check_alpha_max_hw_available] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "ia64-*-*"] {
-    set dg-do-what-default run
-} elseif [is-effective-target arm_neon_ok] {
-    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
-    if [is-effective-target arm_neon_hw] {
-      set dg-do-what-default run
-    } else {
-      set dg-do-what-default compile
-    }
-} else {
+if ![check_vect_support_and_set_flags] {
     return
 }
 

Re: [vect] Ask for review and approving the patch about vect and loongson

[Uros Bizjak]

On Tue, Aug 17, 2010 at 8:37 AM, Mingjie Xing <mingjie.xing@gmail.com> wrote:

>> There are various copies of vect.exp scattered in the testsuite:
>>
>> $ find . -name vect.exp
>> ./gcc.dg/vect/vect.exp
>> ./gfortran.dg/vect/vect.exp
>> ./g++.dg/vect/vect.exp
>>
>> You will need to change them all. Bonus points if you merge all these
>> files into globally accessible support library.
>>
>> Uros.
>>
>
> Thanks for point it out. I've extracted the common piece of code into
> a function. See the attachment. Tested on Intel Pentium.
>
> One problem is that there is a little difference among these vect.exp's,
>
> ==========gcc.dg/vect/vect.exp===========
> } elseif [is-effective-target arm_neon_ok] {
>    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
>    # NEON does not support denormals, so is not used for vectorization by
>    # default to avoid loss of precision.  We must pass -ffast-math to test
>    # vectorization of float operations.
>    lappend DEFAULT_VECTCFLAGS "-ffast-math"
>    if [is-effective-target arm_neon_hw] {
>      set dg-do-what-default run
>    } else {
>      set dg-do-what-default compile
>    }
> } else {
>
> ===========g++.dg/vect/vect.exp, gfortran.dg/vect/vect.exp=========
> } elseif [is-effective-target arm_neon_ok] {
>    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
>    if [is-effective-target arm_neon_hw] {
>      set dg-do-what-default run
>    } else {
>      set dg-do-what-default compile
>    }
> } else {
>
> I'm not sure if this is intentional and how to handle this in that case.

The difference is not intentional, it looks that someone changed only
gcc.dg/vect/vect.exp. So, in case of doubt, simply copy the
functionality from gcc.dg/vect, this should be the master copy for
your function.

+# Check whether the vect tests are supported by the target and set additional
+# target-dependent vector flags, which can be overriden by using dg-options
+# in individual tests. Return 1 if the target supports, 0 otherwise.

... whether the vectorizer tests are supported ... Return 1 if
vectorizer tests are supported by target, 0 otherwise.

Thanks,
Uros.

Re: [vect] Ask for review and approving the patch about vect and loongson

[Mingjie Xing]

[-- Attachment #1: Type: text/plain, Size: 1844 bytes --]

Hello,

2010/8/13 Uros Bizjak <ubizjak@gmail.com>:
> There are various copies of vect.exp scattered in the testsuite:
>
> $ find . -name vect.exp
> ./gcc.dg/vect/vect.exp
> ./gfortran.dg/vect/vect.exp
> ./g++.dg/vect/vect.exp
>
> You will need to change them all. Bonus points if you merge all these
> files into globally accessible support library.
>
> Uros.
>

Thanks for point it out. I've extracted the common piece of code into
a function. See the attachment. Tested on Intel Pentium.

One problem is that there is a little difference among these vect.exp's,

==========gcc.dg/vect/vect.exp===========
} elseif [is-effective-target arm_neon_ok] {
    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
    # NEON does not support denormals, so is not used for vectorization by
    # default to avoid loss of precision.  We must pass -ffast-math to test
    # vectorization of float operations.
    lappend DEFAULT_VECTCFLAGS "-ffast-math"
    if [is-effective-target arm_neon_hw] {
      set dg-do-what-default run
    } else {
      set dg-do-what-default compile
    }
} else {

===========g++.dg/vect/vect.exp, gfortran.dg/vect/vect.exp=========
} elseif [is-effective-target arm_neon_ok] {
    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
    if [is-effective-target arm_neon_hw] {
      set dg-do-what-default run
    } else {
      set dg-do-what-default compile
    }
} else {

I'm not sure if this is intentional and how to handle this in that case.

testsuite/ChangeLog
  * lib/target-supports.exp (check_vect_support_and_set_flags): New
proc to check if the target supports vect tests and set the
target-dependent flags. Check loongson targets.
  * gcc.dg/vect/vect.exp: use check_vect_support_and_set_flags instead.
  * g++.dg/vect/vect.exp: likewise
  * gfortran.dg/vect/vect.exp: likewise

Thanks,

[-- Attachment #2: vect.patch --]
[-- Type: text/x-diff, Size: 12442 bytes --]

Index: gcc.dg/vect/vect.exp
===================================================================
--- gcc.dg/vect/vect.exp	(revision 163291)
+++ gcc.dg/vect/vect.exp	(working copy)
@@ -37,81 +37,7 @@ set save-dg-do-what-default ${dg-do-what
 # Skip these tests for targets that do not support generating vector
 # code.  Set additional target-dependent vector flags, which can be
 # overridden by using dg-options in individual tests.
-if  [istarget "powerpc-*paired*"]  {
-   lappend DEFAULT_VECTCFLAGS "-mpaired"
-    if [check_750cl_hw_available] {
-        set dg-do-what-default run 
-    } else {
-        set dg-do-what-default compile
-    }
-} elseif [istarget "powerpc*-*-*"] {
-    # Skip targets not supporting -maltivec.
-    if ![is-effective-target powerpc_altivec_ok] {
-	return
-    }
-
-    lappend DEFAULT_VECTCFLAGS "-maltivec"
-    if [check_vsx_hw_available]  {
-      lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
-    }
-
-    if [check_vmx_hw_available] {
-	set dg-do-what-default run
-    } else {
-	if [is-effective-target ilp32] {
-	    # Specify a cpu that supports VMX for compile-only tests.
-	    lappend DEFAULT_VECTCFLAGS "-mcpu=970"
-	}
-	set dg-do-what-default compile
-    }
-} elseif { [istarget  "spu-*-*"] } {
-   set dg-do-what-default run
-} elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
-    lappend DEFAULT_VECTCFLAGS "-msse2"
-    if { [check_effective_target_sse2_runtime] } {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
-    set dg-do-what-default run
-} elseif [istarget "sparc*-*-*"] {
-    lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
-    if [check_effective_target_ultrasparc_hw] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "alpha*-*-*"] {
-    # Alpha's vectorization capabilities are extremely limited.
-    # It's more effort than its worth disabling all of the tests
-    # that it cannot pass.  But if you actually want to see what
-    # does work, command out the return.
-    return
-
-    lappend DEFAULT_VECTCFLAGS "-mmax"
-    if [check_alpha_max_hw_available] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "ia64-*-*"] {
-    set dg-do-what-default run
-} elseif [is-effective-target arm_neon_ok] {
-    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
-    # NEON does not support denormals, so is not used for vectorization by
-    # default to avoid loss of precision.  We must pass -ffast-math to test
-    # vectorization of float operations.
-    lappend DEFAULT_VECTCFLAGS "-ffast-math"
-    if [is-effective-target arm_neon_hw] {
-      set dg-do-what-default run
-    } else {
-      set dg-do-what-default compile
-    }
-} else {
+if ![check_vect_support_and_set_flags] {
     return
 }
 
Index: g++.dg/vect/vect.exp
===================================================================
--- g++.dg/vect/vect.exp	(revision 163291)
+++ g++.dg/vect/vect.exp	(working copy)
@@ -45,77 +45,7 @@ lappend DEFAULT_VECTCFLAGS "-O2" "-ftree
 # Skip these tests for targets that do not support generating vector
 # code.  Set additional target-dependent vector flags, which can be
 # overridden by using dg-options in individual tests.
-if  [istarget "powerpc-*paired*"]  {
-   lappend DEFAULT_VECTCFLAGS "-mpaired"
-    if [check_750cl_hw_available] {
-        set dg-do-what-default run 
-    } else {
-        set dg-do-what-default compile
-    }
-} elseif [istarget "powerpc*-*-*"] {
-    # Skip targets not supporting -maltivec.
-    if ![is-effective-target powerpc_altivec_ok] {
-	return
-    }
-
-    lappend DEFAULT_VECTCFLAGS "-maltivec"
-    if [check_vsx_hw_available]  {
-      lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
-    }
-
-    if [check_vmx_hw_available] {
-	set dg-do-what-default run
-    } else {
-	if [is-effective-target ilp32] {
-	    # Specify a cpu that supports VMX for compile-only tests.
-	    lappend DEFAULT_VECTCFLAGS "-mcpu=970"
-	}
-	set dg-do-what-default compile
-    }
-} elseif { [istarget  "spu-*-*"] } {
-   set dg-do-what-default run
-} elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
-    lappend DEFAULT_VECTCFLAGS "-msse2"
-    if { [check_effective_target_sse2_runtime] } {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
-    set dg-do-what-default run
-} elseif [istarget "sparc*-*-*"] {
-    lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
-    if [check_effective_target_ultrasparc_hw] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "alpha*-*-*"] {
-    # Alpha's vectorization capabilities are extremely limited.
-    # It's more effort than its worth disabling all of the tests
-    # that it cannot pass.  But if you actually want to see what
-    # does work, command out the return.
-    return
-
-    lappend DEFAULT_VECTCFLAGS "-mmax"
-    if [check_alpha_max_hw_available] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "ia64-*-*"] {
-    set dg-do-what-default run
-} elseif [is-effective-target arm_neon_ok] {
-    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
-    if [is-effective-target arm_neon_hw] {
-      set dg-do-what-default run
-    } else {
-      set dg-do-what-default compile
-    }
-} else {
+if ![check_vect_support_and_set_flags] {
     return
 }
 
Index: lib/target-supports.exp
===================================================================
--- lib/target-supports.exp	(revision 163291)
+++ lib/target-supports.exp	(working copy)
@@ -3547,3 +3547,96 @@ proc check_effective_target_c++ { } {
     }
  return 0
 }
+
+# Check whether the vect tests are supported by the target and set additional
+# target-dependent vector flags, which can be overriden by using dg-options
+# in individual tests. Return 1 if the target supports, 0 otherwise.
+
+proc check_vect_support_and_set_flags { } {
+    global DEFAULT_VECTCFLAGS
+    global dg-do-what-default
+
+    if  [istarget "powerpc-*paired*"]  {
+        lappend DEFAULT_VECTCFLAGS "-mpaired"
+        if [check_750cl_hw_available] {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } elseif [istarget "powerpc*-*-*"] {
+        # Skip targets not supporting -maltivec.
+        if ![is-effective-target powerpc_altivec_ok] {
+            return 0
+        }
+
+        lappend DEFAULT_VECTCFLAGS "-maltivec"
+        if [check_vsx_hw_available]  {
+            lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
+        }
+
+        if [check_vmx_hw_available] {
+            set dg-do-what-default run
+        } else {
+            if [is-effective-target ilp32] {
+                # Specify a cpu that supports VMX for compile-only tests.
+                lappend DEFAULT_VECTCFLAGS "-mcpu=970"
+            }
+            set dg-do-what-default compile
+        }
+    } elseif { [istarget  "spu-*-*"] } {
+        set dg-do-what-default run
+    } elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
+        lappend DEFAULT_VECTCFLAGS "-msse2"
+        if { [check_effective_target_sse2_runtime] } {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } elseif { [istarget "mips*-*-*"]
+               && ([check_effective_target_mpaired_single]
+                    || [check_effective_target_mips_loongson])
+               && [check_effective_target_nomips16] } {
+        if { [check_effective_target_mpaired_single] } {
+            lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+        }
+        set dg-do-what-default run
+    } elseif [istarget "sparc*-*-*"] {
+        lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
+        if [check_effective_target_ultrasparc_hw] {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } elseif [istarget "alpha*-*-*"] {
+        # Alpha's vectorization capabilities are extremely limited.
+        # It's more effort than its worth disabling all of the tests
+        # that it cannot pass.  But if you actually want to see what
+        # does work, command out the return.
+        return 0
+
+        lappend DEFAULT_VECTCFLAGS "-mmax"
+        if [check_alpha_max_hw_available] {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } elseif [istarget "ia64-*-*"] {
+        set dg-do-what-default run
+    } elseif [is-effective-target arm_neon_ok] {
+        eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
+        # NEON does not support denormals, so is not used for vectorization by
+        # default to avoid loss of precision.  We must pass -ffast-math to test
+        # vectorization of float operations.
+        lappend DEFAULT_VECTCFLAGS "-ffast-math"
+        if [is-effective-target arm_neon_hw] {
+            set dg-do-what-default run
+        } else {
+            set dg-do-what-default compile
+        }
+    } else {
+        return 0
+    }
+
+    return 1
+}
+
Index: gfortran.dg/vect/vect.exp
===================================================================
--- gfortran.dg/vect/vect.exp	(revision 163291)
+++ gfortran.dg/vect/vect.exp	(working copy)
@@ -38,77 +38,7 @@ set save-dg-do-what-default ${dg-do-what
 # Skip these tests for targets that do not support generating vector
 # code.  Set additional target-dependent vector flags, which can be
 # overridden by using dg-options in individual tests.
-if  [istarget "powerpc-*paired*"]  {
-   lappend DEFAULT_VECTCFLAGS "-mpaired"
-    if [check_750cl_hw_available] {
-        set dg-do-what-default run 
-    } else {
-        set dg-do-what-default compile
-    }
-} elseif [istarget "powerpc*-*-*"] {
-    # Skip targets not supporting -maltivec.
-    if ![is-effective-target powerpc_altivec_ok] {
-	return
-    }
-
-    lappend DEFAULT_VECTCFLAGS "-maltivec"
-    if [check_vsx_hw_available]  {
-      lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign"
-    }
-
-    if [check_vmx_hw_available] {
-	set dg-do-what-default run
-    } else {
-	if [is-effective-target ilp32] {
-	    # Specify a cpu that supports VMX for compile-only tests.
-	    lappend DEFAULT_VECTCFLAGS "-mcpu=970"
-	}
-	set dg-do-what-default compile
-    }
-} elseif { [istarget  "spu-*-*"] } {
-   set dg-do-what-default run
-} elseif { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } {
-    lappend DEFAULT_VECTCFLAGS "-msse2"
-    if { [check_effective_target_sse2_runtime] } {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
-    set dg-do-what-default run
-} elseif [istarget "sparc*-*-*"] {
-    lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
-    if [check_effective_target_ultrasparc_hw] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "alpha*-*-*"] {
-    # Alpha's vectorization capabilities are extremely limited.
-    # It's more effort than its worth disabling all of the tests
-    # that it cannot pass.  But if you actually want to see what
-    # does work, command out the return.
-    return
-
-    lappend DEFAULT_VECTCFLAGS "-mmax"
-    if [check_alpha_max_hw_available] {
-	set dg-do-what-default run
-    } else {
-	set dg-do-what-default compile
-    }
-} elseif [istarget "ia64-*-*"] {
-    set dg-do-what-default run
-} elseif [is-effective-target arm_neon_ok] {
-    eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
-    if [is-effective-target arm_neon_hw] {
-      set dg-do-what-default run
-    } else {
-      set dg-do-what-default compile
-    }
-} else {
+if ![check_vect_support_and_set_flags] {
     return
 }
 

Re: [vect] Ask for review and approving the patch about vect and loongson

[Richard Sandiford]

Mingjie Xing <mingjie.xing@gmail.com> writes:
> My GCC assignment/disclaimer process with the FSF is currently
> complete. I've put the previously reviewed patches in the attachment
> and changed the contact also.

Great!  Thanks for contributions, and for seeing this through.

I've applied loongson_mult.patch, fast-math-vect-reduc-8.patch and
target-supports.patch.  Uros is right about the other vect.exps;
sorry for not catching that.

Richard

Re: [vect] Ask for review and approving the patch about vect and loongson

[Uros Bizjak]

Hello!

> Mingjie Xing  <mingjie.xing@gmail.com>
>
> gcc/ChangeLog
>  * loongson.md: Change define_insn "loongson_pmull<V_suffix>" to "mul<mode>3".
>  * mips.c: Add "#define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3".
>
> testsuite/ChangeLog
>  * fast-math-vect-reduc-8.c: Move dg-require-effective-target after dg-do.
>  * vect.exp: Run the vect testsuite when the target is loongson*
>  * target-supports.exp: Check loongson target in vector specific attributes.

Index: testsuite/gcc.dg/vect/vect.exp
===================================================================
--- testsuite/gcc.dg/vect/vect.exp	(revision 163219)
+++ testsuite/gcc.dg/vect/vect.exp	(working copy)
@@ -74,9 +74,12 @@ if  [istarget "powerpc-*paired*"]  {
 	set dg-do-what-default compile
     }
 } elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+           && ([check_effective_target_mpaired_single]
+               || [check_effective_target_mips_loongson])
+           && [check_effective_target_nomips16] } {
+    if { [check_effective_target_mpaired_single] } {
+      lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    }
     set dg-do-what-default run
 } elseif [istarget "sparc*-*-*"] {
     lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"

There are various copies of vect.exp scattered in the testsuite:

$ find . -name vect.exp
./gcc.dg/vect/vect.exp
./gfortran.dg/vect/vect.exp
./g++.dg/vect/vect.exp

You will need to change them all. Bonus points if you merge all these
files into globally accessible support library.

Uros.

Re: [vect] Ask for review and approving the patch about vect and loongson

[Mingjie Xing]

[-- Attachment #1: Type: text/plain, Size: 1011 bytes --]

Hello,

> Eric Fisher <joefoxreal@gmail.com> writes:
>> Thanks. I've updated the patch in the attachment.
>
> Watch the formatting: the (match_operand: ...)s should line up vertically.
>
> The patch is OK with that change.  Obviously we'll have to wait until
> the copyright assignment is sorted out before the patches can be applied.
>
> Richard
>

My GCC assignment/disclaimer process with the FSF is currently
complete. I've put the previously reviewed patches in the attachment
and changed the contact also.

Mingjie Xing  <mingjie.xing@gmail.com>

gcc/ChangeLog
 * loongson.md: Change define_insn "loongson_pmull<V_suffix>" to "mul<mode>3".
 * mips.c: Add "#define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3".

testsuite/ChangeLog
 * fast-math-vect-reduc-8.c: Move dg-require-effective-target after dg-do.
 * vect.exp: Run the vect testsuite when the target is loongson*
 * target-supports.exp: Check loongson target in vector specific attributes.

BTW, I don't have write access to svn.

Regards,
Mingjie

[-- Attachment #2: loongson_mult.patch --]
[-- Type: text/x-diff, Size: 1622 bytes --]

Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 163219)
+++ config/mips/loongson.md	(working copy)
@@ -31,7 +31,6 @@
   UNSPEC_LOONGSON_PMOVMSK
   UNSPEC_LOONGSON_PMULHU
   UNSPEC_LOONGSON_PMULH
-  UNSPEC_LOONGSON_PMULL
   UNSPEC_LOONGSON_PMULU
   UNSPEC_LOONGSON_PASUBUB
   UNSPEC_LOONGSON_BIADD
@@ -353,11 +352,10 @@
   [(set_attr "type" "fmul")])
 
 ;; Multiply signed integers and store low result.
-(define_insn "loongson_pmull<V_suffix>"
+(define_insn "mul<mode>3"
   [(set (match_operand:VH 0 "register_operand" "=f")
-        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
-		    (match_operand:VH 2 "register_operand" "f")]
-		   UNSPEC_LOONGSON_PMULL))]
+        (mult:VH (match_operand:VH 1 "register_operand" "f")
+                 (match_operand:VH 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "pmull<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c	(revision 163219)
+++ config/mips/mips.c	(working copy)
@@ -12684,6 +12684,7 @@ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BU
 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
+#define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3

[-- Attachment #3: fast-math-vect-reduc-8.patch --]
[-- Type: text/x-diff, Size: 426 bytes --]

Index: testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c
===================================================================
--- testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c	(revision 163219)
+++ testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c	(working copy)
@@ -1,5 +1,5 @@
-/* { dg-require-effective-target vect_float } */
 /* { dg-do compile } */
+/* { dg-require-effective-target vect_float } */
 
 #include "tree-vect.h"
 

[-- Attachment #4: vect.patch --]
[-- Type: text/x-diff, Size: 892 bytes --]

Index: testsuite/gcc.dg/vect/vect.exp
===================================================================
--- testsuite/gcc.dg/vect/vect.exp	(revision 163219)
+++ testsuite/gcc.dg/vect/vect.exp	(working copy)
@@ -74,9 +74,12 @@ if  [istarget "powerpc-*paired*"]  {
 	set dg-do-what-default compile
     }
 } elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+           && ([check_effective_target_mpaired_single]
+               || [check_effective_target_mips_loongson])
+           && [check_effective_target_nomips16] } {
+    if { [check_effective_target_mpaired_single] } {
+      lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    }
     set dg-do-what-default run
 } elseif [istarget "sparc*-*-*"] {
     lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"

[-- Attachment #5: target-supports.patch --]
[-- Type: text/x-diff, Size: 2178 bytes --]

Index: testsuite/lib/target-supports.exp
===================================================================
--- testsuite/lib/target-supports.exp	(revision 163219)
+++ testsuite/lib/target-supports.exp	(working copy)
@@ -1620,7 +1620,9 @@ proc check_effective_target_vect_int { }
 	      || [istarget sparc*-*-*]
 	      || [istarget alpha*-*-*]
 	      || [istarget ia64-*-*] 
-	      || [check_effective_target_arm32] } {
+	      || [check_effective_target_arm32]
+	      || ([istarget mips*-*-*]
+	           && [check_effective_target_mips_loongson]) } {
 	   set et_vect_int_saved 1
 	}
     }
@@ -2156,7 +2158,9 @@ proc check_effective_target_vect_shift {
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
-	     || [check_effective_target_arm32] } {
+	     || [check_effective_target_arm32]
+	     || ([istarget mips*-*-*]
+	          && [check_effective_target_mips_loongson]) } {
 	   set et_vect_shift_saved 1
 	}
     }
@@ -2270,7 +2274,9 @@ proc check_effective_target_vect_no_int_
 	set et_vect_no_int_max_saved 0
 	if { [istarget sparc*-*-*]
 	     || [istarget spu-*-*]
-	     || [istarget alpha*-*-*] } {
+	     || [istarget alpha*-*-*]
+	     || ([istarget mips*-*-*]
+	          && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_int_max_saved 1
 	}
     }
@@ -2643,7 +2649,9 @@ proc check_effective_target_vect_no_alig
 	if { [istarget mipsisa64*-*-*]
 	     || [istarget sparc*-*-*]
 	     || [istarget ia64-*-*]
-	     || [check_effective_target_arm32] } { 
+	     || [check_effective_target_arm32]
+	     || ([istarget mips*-*-*]
+	          && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_align_saved 1
 	}
     }
@@ -2833,8 +2841,10 @@ proc check_effective_target_vect_short_m
 	     || [istarget spu-*-*]
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
-             || [istarget powerpc*-*-*]
-             || [check_effective_target_arm32] } {
+	     || [istarget powerpc*-*-*]
+	     || [check_effective_target_arm32]
+	     || ([istarget mips*-*-*]
+	          && [check_effective_target_mips_loongson]) } {
 	   set et_vect_short_mult_saved 1
 	}
     }