From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 49730 invoked by alias); 15 Dec 2015 10:54:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 49693 invoked by uid 89); 15 Dec 2015 10:54:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 15 Dec 2015 10:54:55 +0000 Received: from emea01-am1-obe.outbound.protection.outlook.com (mail-am1lrp0014.outbound.protection.outlook.com [213.199.154.14]) (Using TLS) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-17-HmaWI5aOTG2tFaCPgcIRRw-1; Tue, 15 Dec 2015 10:54:50 +0000 Received: from AM3PR08MB0088.eurprd08.prod.outlook.com (2a01:111:e400:8847::18) by AM3PR08MB0594.eurprd08.prod.outlook.com (2a01:111:e400:c408::16) with Microsoft SMTP Server (TLS) id 15.1.355.16; Tue, 15 Dec 2015 10:54:49 +0000 Received: from AM3PR08MB0088.eurprd08.prod.outlook.com ([fe80::5c7b:335e:6049:3647]) by AM3PR08MB0088.eurprd08.prod.outlook.com ([fe80::5c7b:335e:6049:3647%14]) with mapi id 15.01.0355.012; Tue, 15 Dec 2015 10:54:49 +0000 From: Wilco Dijkstra To: James Greenhalgh CC: "gcc-patches@gcc.gnu.org" , nd Subject: RE: [PATCH][AArch64] Add TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS Date: Tue, 15 Dec 2015 10:54:00 -0000 Message-ID: x-microsoft-exchange-diagnostics: 1;AM3PR08MB0594;5:ZzUDV94qxPyx7b5fl6p55NSpb4t//MrWqaPe0Mz9f108UuCJ/FrRy+dpscSNQwoelCwKvZpufBvWFeEcFh9RbHUw8qevdBzR0EdTLLAZW04+ioRz5pBqpPqqlXRMmBzbyalAVWEwW+Pkkb3U8kZGfQ==;24:acrw8Yyo90np3GsFRpmsB8kIBiXe2TAcA2M6OM/jstRE4R/Aw8gGc5qbJdsye2cr5TJm8wvlSXV+xyXeHIU/yq136Eslysv/Zuu/0wslwcw=;20:C4d7hUirMYYjmkx4Bpi+zsmkuexzQRxKljbF0HJWtiYMmWASwoOiztBkDZK647tB06OFajik0WEAhX+Iorrl/dOEb6GmQzyWykWuXxyAU+IvNOsukRiPzHZbABNl2dAYd3hiCfeFhFyUdfPCgUjqVJ3M1UgRQ9xMdNSemWvhcp8= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM3PR08MB0594; nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(2401047)(8121501046)(520078)(5005006)(10201501046)(3002001);SRVR:AM3PR08MB0594;BCL:0;PCL:0;RULEID:;SRVR:AM3PR08MB0594; x-forefront-prvs: 07915F544A x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(54534003)(189002)(377424004)(13464003)(199003)(86362001)(110136002)(87936001)(11100500001)(106356001)(5250100002)(5004730100002)(3846002)(6116002)(74316001)(586003)(1220700001)(5008740100001)(102836003)(105586002)(1096002)(40100003)(101416001)(2900100001)(33656002)(97736004)(92566002)(5003600100002)(54356999)(76576001)(19580405001)(50986999)(81156007)(5002640100001)(450100001)(19580395003)(189998001)(5001960100002)(66066001);DIR:OUT;SFP:1101;SCL:1;SRVR:AM3PR08MB0594;H:AM3PR08MB0088.eurprd08.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Dec 2015 10:54:49.1269 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0594 X-MC-Unique: HmaWI5aOTG2tFaCPgcIRRw-1 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-SW-Source: 2015-12/txt/msg01465.txt.bz2 ping > -----Original Message----- > From: Wilco Dijkstra [mailto:Wilco.Dijkstra@arm.com] > Sent: 06 November 2015 20:06 > To: 'gcc-patches@gcc.gnu.org' > Subject: [PATCH][AArch64] Add TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS >=20 > This patch adds support for the TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS ho= ok. When the cost of GENERAL_REGS and > FP_REGS is identical, the register allocator always uses ALL_REGS even wh= en it has a much higher cost. The hook changes the class to > either FP_REGS or GENERAL_REGS depending on the mode of the register. Thi= s results in better register allocation overall, fewer spills > and reduced codesize - particularly in SPEC2006 gamess. >=20 > GCC regression passes with several minor fixes. >=20 > OK for commit? >=20 > ChangeLog: > 2015-11-06 Wilco Dijkstra >=20 > * gcc/config/aarch64/aarch64.c > (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): New define. > (aarch64_ira_change_pseudo_allocno_class): New function. > * gcc/testsuite/gcc.target/aarch64/cvtf_1.c: Build with -O2. > * gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c > (test_corners_sisd_di): Improve force to SIMD register. > (test_corners_sisd_si): Likewise. > * gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c: Build with -O2. > * gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c: > Remove scan-assembler check for ldr. >=20 > -- > gcc/config/aarch64/aarch64.c | 22 ++++++++++++++++= ++++++ > gcc/testsuite/gcc.target/aarch64/cvtf_1.c | 2 +- > gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c | 4 ++-- > gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c | 2 +- > .../gcc.target/aarch64/vect-ld1r-compile-fp.c | 1 - > 5 files changed, 26 insertions(+), 5 deletions(-) >=20 > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index 6da7245..9b60666 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -597,6 +597,24 @@ aarch64_err_no_fpadvsimd (machine_mode mode, const c= har *msg) > error ("%qs feature modifier is incompatible with %s %s", "+nofp", m= c, msg); > } >=20 > +/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. > + The register allocator chooses ALL_REGS if FP_REGS and GENERAL_REGS h= ave > + the same cost even if ALL_REGS has a much larger cost. This results = in bad > + allocations and spilling. To avoid this we force the class to GENERA= L_REGS > + if the mode is integer. */ > + > +static reg_class_t > +aarch64_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_= class) > +{ > + enum machine_mode mode; > + > + if (allocno_class !=3D ALL_REGS) > + return allocno_class; > + > + mode =3D PSEUDO_REGNO_MODE (regno); > + return FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode) ? FP_REGS : GENERAL= _REGS; > +} > + > static unsigned int > aarch64_min_divisions_for_recip_mul (enum machine_mode mode) > { > @@ -13113,6 +13131,10 @@ aarch64_promoted_type (const_tree t) > #undef TARGET_INIT_BUILTINS > #define TARGET_INIT_BUILTINS aarch64_init_builtins >=20 > +#undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS > +#define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \ > + aarch64_ira_change_pseudo_allocno_class > + > #undef TARGET_LEGITIMATE_ADDRESS_P > #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p >=20 > diff --git a/gcc/testsuite/gcc.target/aarch64/cvtf_1.c b/gcc/testsuite/gc= c.target/aarch64/cvtf_1.c > index 5f2ff81..96501db 100644 > --- a/gcc/testsuite/gcc.target/aarch64/cvtf_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/cvtf_1.c > @@ -1,5 +1,5 @@ > /* { dg-do run } */ > -/* { dg-options "-save-temps -fno-inline -O1" } */ > +/* { dg-options "-save-temps -fno-inline -O2" } */ >=20 > #define FCVTDEF(ftype,itype) \ > void \ > diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c b/gcc/test= suite/gcc.target/aarch64/scalar_shift_1.c > index 363f554..8465c89 100644 > --- a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c > @@ -186,9 +186,9 @@ test_corners_sisd_di (Int64x1 b) > { > force_simd_di (b); > b =3D b >> 63; > + force_simd_di (b); > b =3D b >> 0; > b +=3D b >> 65; /* { dg-warning "right shift count >=3D width of type"= } */ > - force_simd_di (b); >=20 > return b; > } > @@ -199,9 +199,9 @@ test_corners_sisd_si (Int32x1 b) > { > force_simd_si (b); > b =3D b >> 31; > + force_simd_si (b); > b =3D b >> 0; > b +=3D b >> 33; /* { dg-warning "right shift count >=3D width of type"= } */ > - force_simd_si (b); >=20 > return b; > } > diff --git a/gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c b/gcc/testsui= te/gcc.target/aarch64/vdup_lane_2.c > index a49db3e..c5a9c52 100644 > --- a/gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c > +++ b/gcc/testsuite/gcc.target/aarch64/vdup_lane_2.c > @@ -1,6 +1,6 @@ > /* Test vdup_lane intrinsics work correctly. */ > /* { dg-do run } */ > -/* { dg-options "-O1 --save-temps" } */ > +/* { dg-options "-O2 --save-temps" } */ >=20 > #include >=20 > diff --git a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c b/gc= c/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c > index 66e0168..4711c61 100644 > --- a/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c > +++ b/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c > @@ -8,6 +8,5 @@ DEF (float) > DEF (double) >=20 > /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */ > -/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */ > /* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */ >=20 > -- > 1.8.3