Re: [PATCH][AArch64] Replace insn to zero up DF register

[Wilco Dijkstra <Wilco.Dijkstra@arm.com>]

On 12/16/2015 03:30 PM, Evandro Menezes wrote:
>
>    On 10/30/2015 05:24 AM, Marcus Shawcroft wrote:
>
>        On 20 October 2015 at 00:40, Evandro Menezes <e.menezes@samsung.com> wrote:
>
>            In the existing targets, it seems that it's always faster to zero up a DF
>
>            register with "movi %d0, #0" instead of "fmov %d0, xzr".
>
>            This patch modifies the respective pattern.
>
>
>        Hi Evandro,
>
>        This patch changes the generic, u architecture independent instruction
>        selection. The ARM ARM (C3.5.3) makes a specific recommendation about
>        the choice of instruction in this situation and the current
>        implementation in GCC follows that recommendation.  Wilco has also
>        picked up on this issue he has the same patch internal to ARM along
>        with an ongoing discussion with ARM architecture folk regarding this
>        recommendation.  I'm reluctant to take this patch right now on the
>        basis that it runs contrary to ARM ARM recommendation pending the
>        conclusion of Wilco's discussion with ARM architecture folk.
>
>
>    Have you had a chance to discuss this internally further?

Yes, it was decided to remove the recommendation from future ARM ARM's.

Several review comments on your patch (https://patchwork.ozlabs.org/patch/532736):

* This should be added to movhf, movsf and movdf - movtf already does this.
* It is important to set the "fp" and "simd" attributes so that the movi variant can
   only be selected if it is available.

Cheers,
Wilco