From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 103173 invoked by alias); 22 Jan 2016 13:52:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 103154 invoked by uid 89); 22 Jan 2016 13:52:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 spammy=recommendation, fmov, xzr, picked X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 22 Jan 2016 13:52:10 +0000 Received: from emea01-am1-obe.outbound.protection.outlook.com (mail-am1lrp0017.outbound.protection.outlook.com [213.199.154.17]) (Using TLS) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-30-ZWX_1H8cT1K8_yDJr_MGxg-1; Fri, 22 Jan 2016 13:52:04 +0000 Received: from AM3PR08MB0088.eurprd08.prod.outlook.com (2a01:111:e400:8847::18) by AM3PR08MB0593.eurprd08.prod.outlook.com (2a01:111:e400:c408::15) with Microsoft SMTP Server (TLS) id 15.1.390.13; Fri, 22 Jan 2016 13:52:01 +0000 Received: from AM3PR08MB0088.eurprd08.prod.outlook.com ([fe80::9820:2c1d:325d:6c0f]) by AM3PR08MB0088.eurprd08.prod.outlook.com ([fe80::9820:2c1d:325d:6c0f%18]) with mapi id 15.01.0390.013; Fri, 22 Jan 2016 13:52:01 +0000 From: Wilco Dijkstra To: Evandro Menezes CC: "gcc-patches@gcc.gnu.org" , nd , Marcus Shawcroft , Kyrylo Tkachov , James Greenhalgh Subject: Re: [PATCH][AArch64] Replace insn to zero up DF register Date: Fri, 22 Jan 2016 13:52:00 -0000 Message-ID: x-microsoft-exchange-diagnostics: 1;AM3PR08MB0593;5:rlwx/7/k5OX6pOSjnboqE8kxVivsWMjSRCYSqgLFEhrBEyKfhR73+91dhGRurnSb73HJP1tfFiWXoPId1Zga8PE5PTbMNlwGR39naOx9ceiGXLH4OzIu3uJ14AOSmvP1k1c4NyEndxYfCUOOApfCEQ==;24:sFqDG+dQzhJ1Xfu39VUk39UoTeYYMAMX3UJDOaJfQyXruEompOLtsWj0yOzaipFUwgMLI5h67Pj67D1BrzZrvUO+gpe+8PM4PVLtJY5njHI=;20:9BKyI/gC00+zomYTrXKcfKBwF17A1tuMs7poOZlXClOpC8AuTQ27Lb/xP9WMeAHgcFtjIBgbSeHDtHgj7EXyNZ/kC2h/JGYMDfqq//7b9fJLKZuGJVR0hLZ6N7mMJs3TeNRWstBTeNYCJ0sNeIoBjz+l6NYshjWzyX9PezzhDdk= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:AM3PR08MB0593; x-ms-office365-filtering-correlation-id: 63bda098-c7c5-4e10-2b17-08d323333448 nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(123027)(601004)(2401047)(8121501046)(5005006)(520078)(10201501046)(3002001);SRVR:AM3PR08MB0593;BCL:0;PCL:0;RULEID:;SRVR:AM3PR08MB0593; x-forefront-prvs: 08296C9B35 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(979002)(6009001)(377454003)(24454002)(479174004)(199003)(189002)(87936001)(2906002)(5001960100002)(33656002)(5250100002)(40100003)(5004730100002)(11100500001)(110136002)(54356999)(19580405001)(97736004)(19580395003)(81156007)(106116001)(86362001)(50986999)(2900100001)(92566002)(15975445007)(1096002)(586003)(76576001)(6116002)(1220700001)(102836003)(106356001)(105586002)(3846002)(5002640100001)(101416001)(5003600100002)(189998001)(74316001)(66066001)(5008740100001)(4326007)(969003)(989001)(999001)(1009001)(1019001);DIR:OUT;SFP:1101;SCL:1;SRVR:AM3PR08MB0593;H:AM3PR08MB0088.eurprd08.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jan 2016 13:52:01.0883 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0593 X-MC-Unique: ZWX_1H8cT1K8_yDJr_MGxg-1 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-SW-Source: 2016-01/txt/msg01749.txt.bz2 On 12/16/2015 03:30 PM, Evandro Menezes wrote: > >=A0=A0=A0 On 10/30/2015 05:24 AM, Marcus Shawcroft wrote: > >=A0=A0=A0=A0=A0=A0=A0 On 20 October 2015 at 00:40, Evandro Menezes wrote: > >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 In the existing targets, it seems that i= t's always faster to zero up a DF > >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 register with "movi %d0, #0" instead of = "fmov %d0, xzr". > >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 This patch modifies the respective patte= rn. > > >=A0=A0=A0=A0=A0=A0=A0 Hi Evandro, > >=A0=A0=A0=A0=A0=A0=A0 This patch changes the generic, u architecture indep= endent instruction >=A0=A0=A0=A0=A0=A0=A0 selection. The ARM ARM (C3.5.3) makes a specific rec= ommendation about >=A0=A0=A0=A0=A0=A0=A0 the choice of instruction in this situation and the = current >=A0=A0=A0=A0=A0=A0=A0 implementation in GCC follows that recommendation.= =A0 Wilco has also >=A0=A0=A0=A0=A0=A0=A0 picked up on this issue he has the same patch intern= al to ARM along >=A0=A0=A0=A0=A0=A0=A0 with an ongoing discussion with ARM architecture fol= k regarding this >=A0=A0=A0=A0=A0=A0=A0 recommendation.=A0 I'm reluctant to take this patch = right now on the >=A0=A0=A0=A0=A0=A0=A0 basis that it runs contrary to ARM ARM recommendatio= n pending the >=A0=A0=A0=A0=A0=A0=A0 conclusion of Wilco's discussion with ARM architectu= re folk. > > >=A0=A0=A0 Have you had a chance to discuss this internally further? Yes, it was decided to remove the recommendation from future ARM ARM's. Several review comments on your patch (https://patchwork.ozlabs.org/patch/5= 32736): * This should be added to movhf, movsf and movdf - movtf already does this. * It is important to set the "fp" and "simd" attributes so that the movi va= riant can only be selected if it is available. Cheers, Wilco