* ARM Patch Ping
@ 2017-08-01 14:33 Bernd Edlinger
0 siblings, 0 replies; 6+ messages in thread
From: Bernd Edlinger @ 2017-08-01 14:33 UTC (permalink / raw)
To: gcc-patches
Hi,
I would like to kindly remind you of the following patches,
which are already waiting for over 6 months:
[PATCH, ARM] correctly encode the CC reg data flow
https://gcc.gnu.org/ml/gcc-patches/2017-01/msg01351.html
[PATCH, ARM] Further improve stack usage in sha512 (PR 77308)
https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01567.html
[PATCH, ARM] Further improve stack usage in sha512, part 2 (PR 77308)
https://gcc.gnu.org/ml/gcc-patches/2017-04/msg01568.html
I boot-strapped and reg-tested the patches on last week's snapshot to
verify they still apply.
Thanks
Bernd.
^ permalink raw reply [flat|nested] 6+ messages in thread
[parent not found: <59a21f0e-7741-f692-8c6d-1d42e5d8f428@hotmail.de>]
* ARM patch ping
@ 2021-02-19 10:45 Jakub Jelinek
2021-02-19 11:45 ` Kyrylo Tkachov
0 siblings, 1 reply; 6+ messages in thread
From: Jakub Jelinek @ 2021-02-19 10:45 UTC (permalink / raw)
To: Richard Sandiford, Richard Earnshaw, Ramana Radhakrishnan,
Kyrylo Tkachov
Cc: gcc-patches
Hi!
I'd like to ping the
https://gcc.gnu.org/pipermail/gcc-patches/2021-February/565225.html
patch - PR98998 P1 fix.
Thanks
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: ARM patch ping
2021-02-19 10:45 ARM patch ping Jakub Jelinek
@ 2021-02-19 11:45 ` Kyrylo Tkachov
0 siblings, 0 replies; 6+ messages in thread
From: Kyrylo Tkachov @ 2021-02-19 11:45 UTC (permalink / raw)
To: Jakub Jelinek, Richard Sandiford, Richard Earnshaw, Ramana Radhakrishnan
Cc: gcc-patches
Hi Jakub,
> -----Original Message-----
> From: Jakub Jelinek <jakub@redhat.com>
> Sent: 19 February 2021 10:45
> To: Richard Sandiford <Richard.Sandiford@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Ramana Radhakrishnan
> <Ramana.Radhakrishnan@arm.com>; Kyrylo Tkachov
> <Kyrylo.Tkachov@arm.com>
> Cc: gcc-patches@gcc.gnu.org
> Subject: ARM patch ping
>
> Hi!
>
> I'd like to ping the
> https://gcc.gnu.org/pipermail/gcc-patches/2021-February/565225.html
> patch - PR98998 P1 fix.
The patch is okay, but I think we can add a testcase in gcc.target/arm/pure-code/ as Christophe says in the PR.
That should skip it on incompatible configurations.
Thanks,
Kyrill
>
> Thanks
>
> Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* [committed 0/7] Arm: mitigation for AES erratum on Cortex-a57 and Cortex-A72
@ 2022-01-20 11:27 Richard Earnshaw
2022-01-20 11:27 ` [PATCH 3/7] arm: Add option for mitigating against Cortex-A CPU erratum for AES Richard Earnshaw
0 siblings, 1 reply; 6+ messages in thread
From: Richard Earnshaw @ 2022-01-20 11:27 UTC (permalink / raw)
To: GCC patches; +Cc: Richard Earnshaw
The Cortex-A57 and Cortex-A72 processors have an erratum (#1742098
and #1655431 respectively) when running in Arm (32-bit) mode where an
instruction producing a 32-bit result that feeds into an AES encode or
decode can lead to an incorrect result. The erratum does not occur when
operating in 64-bit (aarch64) mode.
The mitigation approach taken by this patch series is in two parts.
Firstly, to ensure that this cannot happen by inserting a special
128-bit copy operation before each operand to a potentially vulnerable
sequence. This is overkill, but safe. The copy operations are
independent instructions, so can be migrated out of loops by the GCSE
pass or other optimizations.
Secondly, we then allow the copy operations to be merged with common
cases where the producer is known to be unaffected by the erratum.
Currently that includes other AES instructions, loads and certain move
operations.
In combination this eliminates the majority of redundant instructions
for normal use cases. I did consider adding a custom pass to do late
insertion of the mitigation, but decided against it. A trivial
implemenation would be unable to hoist operations out of the loop, while
a more complex implementation would require a lot of data-flow
analysis to find the optimum location for each mitigation and might
need to insert mitigation instructions on multiple paths. The pass
would be complex and likely to have difficult to test corner cases.
The series consists of 7 patches. The first two patches are cleanups
to the existing code. Patch 3 adds the command line options to enable
the mitigation and the corresponding documentation. Patch 4 adds the
basic mitigation operation and patches 5 and 6 add various additional
patterns to elide the mitigation for common cases where it is not
needed. The final patch adds a testcase.
Richard Earnshaw (7):
arm: Disambiguate multiple crypto patterns with the same name.
arm: Consistently use crypto_mode attribute in crypto patterns
arm: Add option for mitigating against Cortex-A CPU erratum for AES
arm: add basic mitigation for Cortex-A AES errata
arm: suppress aes erratum when forwarding from aes
arm: elide some cases where the AES erratum workaround is not
required.
arm: Add test for AES erratum mitigation
gcc/config/arm/arm-cpus.in | 9 +-
gcc/config/arm/arm.cc | 9 +
gcc/config/arm/arm.opt | 10 +
gcc/config/arm/crypto.md | 227 ++++++++++++++----
gcc/config/arm/unspecs.md | 1 +
gcc/doc/invoke.texi | 11 +
.../gcc.target/arm/crypto-vaese-erratum1.c | 28 +++
7 files changed, 242 insertions(+), 53 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arm/crypto-vaese-erratum1.c
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/7] arm: Add option for mitigating against Cortex-A CPU erratum for AES
2022-01-20 11:27 [committed 0/7] Arm: mitigation for AES erratum on Cortex-a57 and Cortex-A72 Richard Earnshaw
@ 2022-01-20 11:27 ` Richard Earnshaw
2022-01-27 10:07 ` Jakub Jelinek
0 siblings, 1 reply; 6+ messages in thread
From: Richard Earnshaw @ 2022-01-20 11:27 UTC (permalink / raw)
To: GCC patches; +Cc: Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 880 bytes --]
Add a new option -mfix-cortex-a-aes for enabling the Cortex-A AES
erratum work-around and enable it automatically for the affected
products (Cortex-A57 and Cortex-A72).
gcc/ChangeLog:
* config/arm/arm-cpus.in (quirk_aes_1742098): New quirk feature
(ALL_QUIRKS): Add it.
(cortex-a57, cortex-a72): Enable it.
(cortex-a57.cortex-a53, cortex-a72.cortex-a53): Likewise.
* config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line
option.
(mfix-cortex-a72-aes-1655431): New option alias.
* config/arm/arm.cc (arm_option_override): Handle default settings
for AES erratum switch.
* doc/invoke.texi (Arm Options): Document new options.
---
gcc/config/arm/arm-cpus.in | 9 ++++++++-
gcc/config/arm/arm.cc | 9 +++++++++
gcc/config/arm/arm.opt | 10 ++++++++++
gcc/doc/invoke.texi | 11 +++++++++++
4 files changed, 38 insertions(+), 1 deletion(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0003-arm-Add-option-for-mitigating-against-Cortex-A-CPU-e.patch --]
[-- Type: text/x-patch; name="0003-arm-Add-option-for-mitigating-against-Cortex-A-CPU-e.patch", Size: 4423 bytes --]
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 499e82d790d..0d3082b569f 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -192,6 +192,9 @@ define feature quirk_cm3_ldrd
# v8-m/v8.1-m VLLDM errata.
define feature quirk_vlldm
+# AES errata on some Cortex-A parts
+define feature quirk_aes_1742098
+
# Don't use .cpu assembly directive
define feature quirk_no_asmcpu
@@ -329,7 +332,7 @@ define implied vfp_base MVE MVE_FP ALL_FP
# architectures.
# xscale isn't really a 'quirk', but it isn't an architecture either and we
# need to ignore it for matching purposes.
-define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd quirk_vlldm xscale quirk_no_asmcpu
+define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd quirk_vlldm xscale quirk_no_asmcpu quirk_aes_1742098
define fgroup IGNORE_FOR_MULTILIB cdecp0 cdecp1 cdecp2 cdecp3 cdecp4 cdecp5 cdecp6 cdecp7
@@ -1342,6 +1345,7 @@ begin cpu cortex-a57
cname cortexa57
tune flags LDSCHED
architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
option crypto add FP_ARMv8 CRYPTO
costs cortex_a57
vendor 41
@@ -1353,6 +1357,7 @@ begin cpu cortex-a72
tune for cortex-a57
tune flags LDSCHED
architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
option crypto add FP_ARMv8 CRYPTO
costs cortex_a57
vendor 41
@@ -1391,6 +1396,7 @@ begin cpu cortex-a57.cortex-a53
tune for cortex-a53
tune flags LDSCHED
architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
option crypto add FP_ARMv8 CRYPTO
costs cortex_a57
end cpu cortex-a57.cortex-a53
@@ -1400,6 +1406,7 @@ begin cpu cortex-a72.cortex-a53
tune for cortex-a53
tune flags LDSCHED
architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
option crypto add FP_ARMv8 CRYPTO
costs cortex_a57
end cpu cortex-a72.cortex-a53
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 7825e364c01..04354b36606 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -3638,6 +3638,15 @@ arm_option_override (void)
fix_vlldm = 0;
}
+ /* Enable fix_aes by default if required. */
+ if (fix_aes_erratum_1742098 == 2)
+ {
+ if (bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_aes_1742098))
+ fix_aes_erratum_1742098 = 1;
+ else
+ fix_aes_erratum_1742098 = 0;
+ }
+
/* Hot/Cold partitioning is not currently supported, since we can't
handle literal pool placement in that case. */
if (flag_reorder_blocks_and_partition)
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index 587fc932f96..2a4f165033a 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -272,6 +272,16 @@ mfix-cmse-cve-2021-35465
Target Var(fix_vlldm) Init(2)
Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465).
+mfix-cortex-a57-aes-1742098
+Target Var(fix_aes_erratum_1742098) Init(2) Save
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
+Arm erratum #1742098
+
+mfix-cortex-a72-aes-1655431
+Target Alias(mfix-cortex-a57-aes-1742098)
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
+Arm erratum #1655431
+
munaligned-access
Target Var(unaligned_access) Init(2) Save
Enable unaligned word and halfword accesses to packed data.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 58751c48b8e..67693d6c5cf 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -812,6 +812,8 @@ Objective-C and Objective-C++ Dialects}.
-mtp=@var{name} -mtls-dialect=@var{dialect} @gol
-mword-relocations @gol
-mfix-cortex-m3-ldrd @gol
+-mfix-cortex-a57-aes-1742098 @gol
+-mfix-cortex-a72-aes-1655431 @gol
-munaligned-access @gol
-mneon-for-64bits @gol
-mslow-flash-data @gol
@@ -21281,6 +21283,15 @@ with overlapping destination and base registers are used. This option avoids
generating these instructions. This option is enabled by default when
@option{-mcpu=cortex-m3} is specified.
+@item -mfix-cortex-a57-aes-1742098
+@itemx -mno-fix-cortex-a57-aes-1742098
+@itemx -mfix-cortex-a72-aes-1655431
+@itemx -mno-fix-cortex-a72-aes-1655431
+Enable (disable) mitigation for an erratum on Cortex-A57 and
+Cortex-A72 that affects the AES cryptographic instructions. This
+option is enabled by default when either @option{-mcpu=cortex-a57} or
+@option{-mcpu=cortex-a72} is specified.
+
@item -munaligned-access
@itemx -mno-unaligned-access
@opindex munaligned-access
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/7] arm: Add option for mitigating against Cortex-A CPU erratum for AES
2022-01-20 11:27 ` [PATCH 3/7] arm: Add option for mitigating against Cortex-A CPU erratum for AES Richard Earnshaw
@ 2022-01-27 10:07 ` Jakub Jelinek
2022-02-03 13:20 ` ARM patch ping Jakub Jelinek
0 siblings, 1 reply; 6+ messages in thread
From: Jakub Jelinek @ 2022-01-27 10:07 UTC (permalink / raw)
To: Richard Earnshaw; +Cc: GCC patches
On Thu, Jan 20, 2022 at 11:27:20AM +0000, Richard Earnshaw via Gcc-patches wrote:
> gcc/ChangeLog:
>
> * config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line
> option.
> (mfix-cortex-a72-aes-1655431): New option alias.
> --- a/gcc/config/arm/arm.opt
> +++ b/gcc/config/arm/arm.opt
> @@ -272,6 +272,16 @@ mfix-cmse-cve-2021-35465
> Target Var(fix_vlldm) Init(2)
> Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465).
>
> +mfix-cortex-a57-aes-1742098
> +Target Var(fix_aes_erratum_1742098) Init(2) Save
> +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> +Arm erratum #1742098
> +
> +mfix-cortex-a72-aes-1655431
> +Target Alias(mfix-cortex-a57-aes-1742098)
> +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> +Arm erratum #1655431
> +
> munaligned-access
> Target Var(unaligned_access) Init(2) Save
> Enable unaligned word and halfword accesses to packed data.
This breaks:
Running /usr/src/gcc/gcc/testsuite/gcc.misc-tests/help.exp ...
FAIL: compiler driver --help=target option(s): "^ +-.*[^:.]$" absent from output: " -mfix-cortex-a57-aes-1742098 Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72. Arm erratum #1742098"
help.exp with help of lib/options.exp tests whether all non-empty descriptions of
options are terminated with . or :.
The following patch fixes that, ok for trunk?
2022-01-27 Jakub Jelinek <jakub@redhat.com>
* config/arm/arm.opt (mfix-cortex-a57-aes-1742098,
mfix-cortex-a72-aes-1655431): Ensure description ends with full stop.
--- gcc/config/arm/arm.opt.jj 2022-01-21 22:43:22.879719389 +0100
+++ gcc/config/arm/arm.opt 2022-01-27 11:02:29.457553296 +0100
@@ -274,13 +274,13 @@ Mitigate issues with VLLDM on some M-pro
mfix-cortex-a57-aes-1742098
Target Var(fix_aes_erratum_1742098) Init(2) Save
-Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
-Arm erratum #1742098
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
+(Arm erratum #1742098).
mfix-cortex-a72-aes-1655431
Target Alias(mfix-cortex-a57-aes-1742098)
-Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
-Arm erratum #1655431
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
+(Arm erratum #1655431).
munaligned-access
Target Var(unaligned_access) Init(2) Save
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* ARM patch ping
2022-01-27 10:07 ` Jakub Jelinek
@ 2022-02-03 13:20 ` Jakub Jelinek
2022-02-03 13:28 ` Richard Biener
0 siblings, 1 reply; 6+ messages in thread
From: Jakub Jelinek @ 2022-02-03 13:20 UTC (permalink / raw)
To: Richard Earnshaw, Ramana Radhakrishnan, Kyrylo Tkachov; +Cc: gcc-patches
Hi!
I'd like to ping the following patch.
Thanks.
On Thu, Jan 27, 2022 at 11:07:26AM +0100, Jakub Jelinek via Gcc-patches wrote:
> On Thu, Jan 20, 2022 at 11:27:20AM +0000, Richard Earnshaw via Gcc-patches wrote:
> > gcc/ChangeLog:
> >
> > * config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line
> > option.
> > (mfix-cortex-a72-aes-1655431): New option alias.
>
> > --- a/gcc/config/arm/arm.opt
> > +++ b/gcc/config/arm/arm.opt
> > @@ -272,6 +272,16 @@ mfix-cmse-cve-2021-35465
> > Target Var(fix_vlldm) Init(2)
> > Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465).
> >
> > +mfix-cortex-a57-aes-1742098
> > +Target Var(fix_aes_erratum_1742098) Init(2) Save
> > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > +Arm erratum #1742098
> > +
> > +mfix-cortex-a72-aes-1655431
> > +Target Alias(mfix-cortex-a57-aes-1742098)
> > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > +Arm erratum #1655431
> > +
> > munaligned-access
> > Target Var(unaligned_access) Init(2) Save
> > Enable unaligned word and halfword accesses to packed data.
>
> This breaks:
> Running /usr/src/gcc/gcc/testsuite/gcc.misc-tests/help.exp ...
> FAIL: compiler driver --help=target option(s): "^ +-.*[^:.]$" absent from output: " -mfix-cortex-a57-aes-1742098 Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72. Arm erratum #1742098"
>
> help.exp with help of lib/options.exp tests whether all non-empty descriptions of
> options are terminated with . or :.
>
> The following patch fixes that, ok for trunk?
>
> 2022-01-27 Jakub Jelinek <jakub@redhat.com>
>
> * config/arm/arm.opt (mfix-cortex-a57-aes-1742098,
> mfix-cortex-a72-aes-1655431): Ensure description ends with full stop.
>
> --- gcc/config/arm/arm.opt.jj 2022-01-21 22:43:22.879719389 +0100
> +++ gcc/config/arm/arm.opt 2022-01-27 11:02:29.457553296 +0100
> @@ -274,13 +274,13 @@ Mitigate issues with VLLDM on some M-pro
>
> mfix-cortex-a57-aes-1742098
> Target Var(fix_aes_erratum_1742098) Init(2) Save
> -Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> -Arm erratum #1742098
> +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
> +(Arm erratum #1742098).
>
> mfix-cortex-a72-aes-1655431
> Target Alias(mfix-cortex-a57-aes-1742098)
> -Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> -Arm erratum #1655431
> +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
> +(Arm erratum #1655431).
>
> munaligned-access
> Target Var(unaligned_access) Init(2) Save
Jakub
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ARM patch ping
2022-02-03 13:20 ` ARM patch ping Jakub Jelinek
@ 2022-02-03 13:28 ` Richard Biener
0 siblings, 0 replies; 6+ messages in thread
From: Richard Biener @ 2022-02-03 13:28 UTC (permalink / raw)
To: Jakub Jelinek
Cc: Richard Earnshaw, Ramana Radhakrishnan, Kyrylo Tkachov, GCC Patches
On Thu, Feb 3, 2022 at 2:21 PM Jakub Jelinek via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi!
>
> I'd like to ping the following patch.
OK (note the patch is obvious IMHO)
Richard.
> Thanks.
>
> On Thu, Jan 27, 2022 at 11:07:26AM +0100, Jakub Jelinek via Gcc-patches wrote:
> > On Thu, Jan 20, 2022 at 11:27:20AM +0000, Richard Earnshaw via Gcc-patches wrote:
> > > gcc/ChangeLog:
> > >
> > > * config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line
> > > option.
> > > (mfix-cortex-a72-aes-1655431): New option alias.
> >
> > > --- a/gcc/config/arm/arm.opt
> > > +++ b/gcc/config/arm/arm.opt
> > > @@ -272,6 +272,16 @@ mfix-cmse-cve-2021-35465
> > > Target Var(fix_vlldm) Init(2)
> > > Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465).
> > >
> > > +mfix-cortex-a57-aes-1742098
> > > +Target Var(fix_aes_erratum_1742098) Init(2) Save
> > > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > > +Arm erratum #1742098
> > > +
> > > +mfix-cortex-a72-aes-1655431
> > > +Target Alias(mfix-cortex-a57-aes-1742098)
> > > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > > +Arm erratum #1655431
> > > +
> > > munaligned-access
> > > Target Var(unaligned_access) Init(2) Save
> > > Enable unaligned word and halfword accesses to packed data.
> >
> > This breaks:
> > Running /usr/src/gcc/gcc/testsuite/gcc.misc-tests/help.exp ...
> > FAIL: compiler driver --help=target option(s): "^ +-.*[^:.]$" absent from output: " -mfix-cortex-a57-aes-1742098 Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72. Arm erratum #1742098"
> >
> > help.exp with help of lib/options.exp tests whether all non-empty descriptions of
> > options are terminated with . or :.
> >
> > The following patch fixes that, ok for trunk?
> >
> > 2022-01-27 Jakub Jelinek <jakub@redhat.com>
> >
> > * config/arm/arm.opt (mfix-cortex-a57-aes-1742098,
> > mfix-cortex-a72-aes-1655431): Ensure description ends with full stop.
> >
> > --- gcc/config/arm/arm.opt.jj 2022-01-21 22:43:22.879719389 +0100
> > +++ gcc/config/arm/arm.opt 2022-01-27 11:02:29.457553296 +0100
> > @@ -274,13 +274,13 @@ Mitigate issues with VLLDM on some M-pro
> >
> > mfix-cortex-a57-aes-1742098
> > Target Var(fix_aes_erratum_1742098) Init(2) Save
> > -Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > -Arm erratum #1742098
> > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
> > +(Arm erratum #1742098).
> >
> > mfix-cortex-a72-aes-1655431
> > Target Alias(mfix-cortex-a57-aes-1742098)
> > -Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
> > -Arm erratum #1655431
> > +Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72
> > +(Arm erratum #1655431).
> >
> > munaligned-access
> > Target Var(unaligned_access) Init(2) Save
>
> Jakub
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-02-03 13:28 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-01 14:33 ARM Patch Ping Bernd Edlinger
[not found] <59a21f0e-7741-f692-8c6d-1d42e5d8f428@hotmail.de>
2017-09-03 9:12 ` Bernd Edlinger
2021-02-19 10:45 ARM patch ping Jakub Jelinek
2021-02-19 11:45 ` Kyrylo Tkachov
2022-01-20 11:27 [committed 0/7] Arm: mitigation for AES erratum on Cortex-a57 and Cortex-A72 Richard Earnshaw
2022-01-20 11:27 ` [PATCH 3/7] arm: Add option for mitigating against Cortex-A CPU erratum for AES Richard Earnshaw
2022-01-27 10:07 ` Jakub Jelinek
2022-02-03 13:20 ` ARM patch ping Jakub Jelinek
2022-02-03 13:28 ` Richard Biener
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