From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28750 invoked by alias); 11 Nov 2016 13:14:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 28740 invoked by uid 89); 11 Nov 2016 13:14:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=yy, ry, YY X-HELO: EUR01-VE1-obe.outbound.protection.outlook.com Received: from mail-ve1eur01on0047.outbound.protection.outlook.com (HELO EUR01-VE1-obe.outbound.protection.outlook.com) (104.47.1.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 11 Nov 2016 13:14:18 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com (10.175.46.18) by AM5PR0802MB2609.eurprd08.prod.outlook.com (10.175.46.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.721.10; Fri, 11 Nov 2016 13:14:15 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) by AM5PR0802MB2610.eurprd08.prod.outlook.com ([10.175.46.18]) with mapi id 15.01.0721.010; Fri, 11 Nov 2016 13:14:15 +0000 From: Wilco Dijkstra To: Richard Earnshaw , GCC Patches CC: nd Subject: Re: [PATCH][AArch64] Improve TI mode address offsets Date: Fri, 11 Nov 2016 13:14:00 -0000 Message-ID: References: ,<5ba4a624-d159-c66d-ac16-d6c60f68b2bf@foss.arm.com> In-Reply-To: <5ba4a624-d159-c66d-ac16-d6c60f68b2bf@foss.arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-microsoft-exchange-diagnostics: 1;AM5PR0802MB2609;7:1Eq57ToxOcY1RUpvGha3jYOvlCRMNNER6sUoI4xGQg3lAuAMFufcZELhpIdufDFbWnvBk8b5PVNUPd+BuMYN3uk5bV1aw56oVGqrw2lyTxWEMZYlaMmF8EImUOtnN5zAChcvsSxQiCeByH3Q70zumvaUlSdR6WXrjw2jcp383pgro/Qd9FwLnNrSW5q6H35rM462vb8i71zscNx4VZkuChFNFOL+YBlf0zAxcmJZzMJXRiZXaCY3D+phMPK6CKfpJ3KU/IDyZJxFsUANHo0vOgFbguJ1VGt5WtefmDRm8ATOLLrH++Cr92UAjdAoIVn5rhl5UovK9CAMFOzcbQQA/SHr8KZiuiufPvLJ26rd84s= x-ms-office365-filtering-correlation-id: d56c6592-0ccf-4371-f1c2-08d40a34a318 x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001);SRVR:AM5PR0802MB2609; nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(6055026);SRVR:AM5PR0802MB2609;BCL:0;PCL:0;RULEID:;SRVR:AM5PR0802MB2609; x-forefront-prvs: 012349AD1C x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(24454002)(189002)(199003)(68736007)(66066001)(5001770100001)(229853002)(87936001)(5660300001)(7696004)(450100001)(2950100002)(97736004)(76576001)(189998001)(86362001)(81166006)(3280700002)(3846002)(586003)(102836003)(6116002)(305945005)(7736002)(8936002)(92566002)(2900100001)(4326007)(7846002)(3660700001)(2906002)(106356001)(106116001)(74316002)(105586002)(81156014)(9686002)(77096005)(54356999)(76176999)(8676002)(122556002)(101416001)(33656002)(50986999);DIR:OUT;SFP:1101;SCL:1;SRVR:AM5PR0802MB2609;H:AM5PR0802MB2610.eurprd08.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Nov 2016 13:14:15.5499 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0802MB2609 X-SW-Source: 2016-11/txt/msg01079.txt.bz2 Richard Earnshaw wrote: > Has this patch been truncated?=A0 The last line above looks to be part-way > through a hunk. Oops sorry, it seems the last few lines are missing. Here is the full versi= on: diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3045e6d6447d5c1860feb51708eeb2a21d2caca9..45f44e96ba9e9d3c8c41d977aa5= 09fa13398a8fd 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4066,7 +4066,8 @@ aarch64_classify_address (struct aarch64_address_info= *info, instruction memory accesses. */ if (mode =3D=3D TImode || mode =3D=3D TFmode) return (aarch64_offset_7bit_signed_scaled_p (DImode, offset) - && offset_9bit_signed_unscaled_p (mode, offset)); + && (offset_9bit_signed_unscaled_p (mode, offset) + || offset_12bit_unsigned_scaled_p (mode, offset))); =20 /* A 7bit offset check because OImode will emit a ldp/stp instruction (only big endian will get here). @@ -4270,18 +4271,19 @@ aarch64_legitimate_address_p (machine_mode mode, rt= x x, /* Split an out-of-range address displacement into a base and offset. Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise to increase opportunities for sharing the base address of different siz= es. - For TI/TFmode and unaligned accesses use a 256-byte range. */ + For unaligned accesses and TI/TF mode use the signed 9-bit range. */ static bool aarch64_legitimize_address_displacement (rtx *disp, rtx *off, machine_mode= mode) { - HOST_WIDE_INT mask =3D GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3fff; + HOST_WIDE_INT offset =3D INTVAL (*disp); + HOST_WIDE_INT base =3D offset & ~(GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3= ffc); =20 - if (mode =3D=3D TImode || mode =3D=3D TFmode || - (INTVAL (*disp) & (GET_MODE_SIZE (mode) - 1)) !=3D 0) - mask =3D 0xff; + if (mode =3D=3D TImode || mode =3D=3D TFmode + || (offset & (GET_MODE_SIZE (mode) - 1)) !=3D 0) + base =3D (offset + 0x100) & ~0x1ff; =20 - *off =3D GEN_INT (INTVAL (*disp) & ~mask); - *disp =3D GEN_INT (INTVAL (*disp) & mask); + *off =3D GEN_INT (base); + *disp =3D GEN_INT (offset - base); return true; } =20 @@ -5148,12 +5150,10 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x *= /, machine_mode mode) x =3D gen_rtx_PLUS (Pmode, base, offset_rtx); } =20 - /* Does it look like we'll need a load/store-pair operation? */ + /* Does it look like we'll need a 16-byte load/store-pair operation?= */ HOST_WIDE_INT base_offset; - if (GET_MODE_SIZE (mode) > 16 - || mode =3D=3D TImode) - base_offset =3D ((offset + 64 * GET_MODE_SIZE (mode)) - & ~((128 * GET_MODE_SIZE (mode)) - 1)); + if (GET_MODE_SIZE (mode) > 16) + base_offset =3D (offset + 0x400) & ~0x7f0; /* For offsets aren't a multiple of the access size, the limit is -256...255. */ else if (offset & (GET_MODE_SIZE (mode) - 1)) @@ -5167,6 +5167,8 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x */,= machine_mode mode) /* Small negative offsets are supported. */ else if (IN_RANGE (offset, -256, 0)) base_offset =3D 0; + else if (mode =3D=3D TImode || mode =3D=3D TFmode) + base_offset =3D (offset + 0x100) & ~0x1ff; /* Use 12-bit offset by access size. */ else base_offset =3D offset & (~0xfff * GET_MODE_SIZE (mode)); diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 24b7288976dd0452f41475e40f02750fc56a2a20..62eda569f9b642ac569a61718d7= debf7eae1b59e 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1094,9 +1094,9 @@ =20 (define_insn "*movti_aarch64" [(set (match_operand:TI 0 - "nonimmediate_operand" "=3Dr, *w,r ,*w,r ,Ump,Ump,*w,m") + "nonimmediate_operand" "=3Dr, *w,r ,*w,r,m,m,*w,m") (match_operand:TI 1 - "aarch64_movti_operand" " rn,r ,*w,*w,Ump,r ,Z , m,*w"))] + "aarch64_movti_operand" " rn,r ,*w,*w,m,r,Z, m,*w"))] "(register_operand (operands[0], TImode) || aarch64_reg_or_zero (operands[1], TImode))" "@ @@ -1211,9 +1211,9 @@ =20 (define_insn "*movtf_aarch64" [(set (match_operand:TF 0 - "nonimmediate_operand" "=3Dw,?&r,w ,?r,w,?w,w,m,?r ,Ump,Ump") + "nonimmediate_operand" "=3Dw,?&r,w ,?r,w,?w,w,m,?r,m ,m") (match_operand:TF 1 - "general_operand" " w,?r, ?r,w ,Y,Y ,m,w,Ump,?r ,Y"))] + "general_operand" " w,?r, ?r,w ,Y,Y ,m,w,m ,?r,Y"))] "TARGET_FLOAT && (register_operand (operands[0], TFmode) || aarch64_reg_or_fp_zero (operands[1], TFmode))" "@ =20