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* [PATCH][ARM] Fix ldrd offsets
@ 2016-11-03 12:21 Wilco Dijkstra
  2016-11-08 14:08 ` Ramana Radhakrishnan
                   ` (2 more replies)
  0 siblings, 3 replies; 12+ messages in thread
From: Wilco Dijkstra @ 2016-11-03 12:21 UTC (permalink / raw)
  To: GCC Patches; +Cc: nd

Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
without -255..4091.  This reduces the number of addressing instructions
when using DI mode operations (such as in PR77308).

Bootstrap & regress OK.

ChangeLog:
2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
	* config/arm/arm.c (arm_legitimate_index_p): Add comment.
	(thumb2_legitimate_index_p): Use correct range for DI/DF mode.
--

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
 	{
 	  HOST_WIDE_INT val = INTVAL (index);
 
+	  /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+	     If vldr is selected it uses arm_coproc_mem_operand.  */
 	  if (TARGET_LDRD)
 	    return val > -256 && val < 256;
 	  else
@@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
       if (code == CONST_INT)
 	{
 	  HOST_WIDE_INT val = INTVAL (index);
-	  /* ??? Can we assume ldrd for thumb2?  */
-	  /* Thumb-2 ldrd only has reg+const addressing modes.  */
-	  /* ldrd supports offsets of +-1020.
-	     However the ldr fallback does not.  */
-	  return val > -256 && val < 256 && (val & 3) == 0;
+	  /* Thumb-2 ldrd only has reg+const addressing modes.
+	     Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+	     If vldr is selected it uses arm_coproc_mem_operand.  */
+	  if (TARGET_LDRD)
+	    return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
+	  else
+	    return IN_RANGE (val, -255, 4095 - 4);
 	}
       else
 	return 0;

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2016-11-03 12:21 [PATCH][ARM] Fix ldrd offsets Wilco Dijkstra
@ 2016-11-08 14:08 ` Ramana Radhakrishnan
  2016-11-11 10:59   ` Wilco Dijkstra
  2016-12-06 15:13 ` Wilco Dijkstra
  2017-04-20 16:07 ` Wilco Dijkstra
  2 siblings, 1 reply; 12+ messages in thread
From: Ramana Radhakrishnan @ 2016-11-08 14:08 UTC (permalink / raw)
  To: Wilco Dijkstra; +Cc: GCC Patches, nd

On Thu, Nov 3, 2016 at 12:20 PM, Wilco Dijkstra <Wilco.Dijkstra@arm.com> wrote:
> Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
> without -255..4091.  This reduces the number of addressing instructions
> when using DI mode operations (such as in PR77308).
>
> Bootstrap & regress OK.
>
> ChangeLog:
> 2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>
>
>     gcc/
>         * config/arm/arm.c (arm_legitimate_index_p): Add comment.
>         (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
> --
>
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
>         {
>           HOST_WIDE_INT val = INTVAL (index);
>
> +         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
> +            If vldr is selected it uses arm_coproc_mem_operand.  */
>           if (TARGET_LDRD)
>             return val > -256 && val < 256;
>           else
> @@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
>        if (code == CONST_INT)
>         {
>           HOST_WIDE_INT val = INTVAL (index);
> -         /* ??? Can we assume ldrd for thumb2?  */
> -         /* Thumb-2 ldrd only has reg+const addressing modes.  */
> -         /* ldrd supports offsets of +-1020.
> -            However the ldr fallback does not.  */
> -         return val > -256 && val < 256 && (val & 3) == 0;
> +         /* Thumb-2 ldrd only has reg+const addressing modes.
> +            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
> +            If vldr is selected it uses arm_coproc_mem_operand.  */
> +         if (TARGET_LDRD)

I suspect this should be : if (TARGET_LDRD && !fix_cm3_ldrd)  - I am a
bit worried about this change because of the non-uniformity with ldr
and the fallout with other places where things may break with this.  I
would like a test with -mcpu=cortex-m3/-mthumb as well for an
arm-none-eabi target to see what the fallout of this change is on that
...


Ramana

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2016-11-08 14:08 ` Ramana Radhakrishnan
@ 2016-11-11 10:59   ` Wilco Dijkstra
  0 siblings, 0 replies; 12+ messages in thread
From: Wilco Dijkstra @ 2016-11-11 10:59 UTC (permalink / raw)
  To: Ramana Radhakrishnan; +Cc: GCC Patches, nd

Ramana Radhakrishnan wrote:
> On Thu, Nov 3, 2016 at 12:20 PM, Wilco Dijkstra <Wilco.Dijkstra@arm.com> wrote:

>           HOST_WIDE_INT val = INTVAL (index);
> -         /* ??? Can we assume ldrd for thumb2?  */
> -         /* Thumb-2 ldrd only has reg+const addressing modes.  */
> -         /* ldrd supports offsets of +-1020.
> -            However the ldr fallback does not.  */
> -         return val > -256 && val < 256 && (val & 3) == 0;
> +         /* Thumb-2 ldrd only has reg+const addressing modes.
> +            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
> +            If vldr is selected it uses arm_coproc_mem_operand.  */
> +         if (TARGET_LDRD)

> I suspect this should be : if (TARGET_LDRD && !fix_cm3_ldrd)  - I am a
> bit worried about this change because of the non-uniformity with ldr
> and the fallout with other places where things may break with this.  I
> would like a test with -mcpu=cortex-m3/-mthumb as well for an
> arm-none-eabi target to see what the fallout of this change is on that

Well it works fine given that Thumb-2 supports add/sub up to 4KB, so
the existing expansion into add+ldrd for the fix_cm3_ldrd case works fine.
I ran a bootstrap with fix_cm3_ldrd forced to true, and that completed without
any issues.

Wilco

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2016-11-03 12:21 [PATCH][ARM] Fix ldrd offsets Wilco Dijkstra
  2016-11-08 14:08 ` Ramana Radhakrishnan
@ 2016-12-06 15:13 ` Wilco Dijkstra
  2016-12-14 16:41   ` Wilco Dijkstra
  2017-04-20 16:07 ` Wilco Dijkstra
  2 siblings, 1 reply; 12+ messages in thread
From: Wilco Dijkstra @ 2016-12-06 15:13 UTC (permalink / raw)
  To: GCC Patches, Ramana Radhakrishnan, James Greenhalgh; +Cc: nd

ping


From: Wilco Dijkstra
Sent: 03 November 2016 12:20
To: GCC Patches
Cc: nd
Subject: [PATCH][ARM] Fix ldrd offsets
    
Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
without -255..4091.  This reduces the number of addressing instructions
when using DI mode operations (such as in PR77308).

Bootstrap & regress OK.

ChangeLog:
2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
        * config/arm/arm.c (arm_legitimate_index_p): Add comment.
        (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
--

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
         {
           HOST_WIDE_INT val = INTVAL (index);
 
+         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
           if (TARGET_LDRD)
             return val > -256 && val < 256;
           else
@@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
       if (code == CONST_INT)
         {
           HOST_WIDE_INT val = INTVAL (index);
-         /* ??? Can we assume ldrd for thumb2?  */
-         /* Thumb-2 ldrd only has reg+const addressing modes.  */
-         /* ldrd supports offsets of +-1020.
-            However the ldr fallback does not.  */
-         return val > -256 && val < 256 && (val & 3) == 0;
+         /* Thumb-2 ldrd only has reg+const addressing modes.
+            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
+         if (TARGET_LDRD)
+           return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
+         else
+           return IN_RANGE (val, -255, 4095 - 4);
         }
       else
         return 0;    

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2016-12-06 15:13 ` Wilco Dijkstra
@ 2016-12-14 16:41   ` Wilco Dijkstra
  2017-01-17 12:12     ` Wilco Dijkstra
  0 siblings, 1 reply; 12+ messages in thread
From: Wilco Dijkstra @ 2016-12-14 16:41 UTC (permalink / raw)
  To: GCC Patches, Ramana Radhakrishnan, Kyrylo Tkachov; +Cc: nd


    
ping


From: Wilco Dijkstra
Sent: 03 November 2016 12:20
To: GCC Patches
Cc: nd
Subject: [PATCH][ARM] Fix ldrd offsets
    
Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
without -255..4091.  This reduces the number of addressing instructions
when using DI mode operations (such as in PR77308).

Bootstrap & regress OK.

ChangeLog:
2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
        * config/arm/arm.c (arm_legitimate_index_p): Add comment.
        (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
--

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
         {
           HOST_WIDE_INT val = INTVAL (index);
 
+         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
           if (TARGET_LDRD)
             return val > -256 && val < 256;
           else
@@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
       if (code == CONST_INT)
         {
           HOST_WIDE_INT val = INTVAL (index);
-         /* ??? Can we assume ldrd for thumb2?  */
-         /* Thumb-2 ldrd only has reg+const addressing modes.  */
-         /* ldrd supports offsets of +-1020.
-            However the ldr fallback does not.  */
-         return val > -256 && val < 256 && (val & 3) == 0;
+         /* Thumb-2 ldrd only has reg+const addressing modes.
+            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
+         if (TARGET_LDRD)
+           return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
+         else
+           return IN_RANGE (val, -255, 4095 - 4);
         }
       else
         return 0;        

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2016-12-14 16:41   ` Wilco Dijkstra
@ 2017-01-17 12:12     ` Wilco Dijkstra
  2017-02-02 14:45       ` Wilco Dijkstra
  0 siblings, 1 reply; 12+ messages in thread
From: Wilco Dijkstra @ 2017-01-17 12:12 UTC (permalink / raw)
  To: GCC Patches, Ramana Radhakrishnan, Kyrylo Tkachov; +Cc: nd

ping


From: Wilco Dijkstra
Sent: 03 November 2016 12:20
To: GCC Patches
Cc: nd
Subject: [PATCH][ARM] Fix ldrd offsets
    
Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
without -255..4091.  This reduces the number of addressing instructions
when using DI mode operations (such as in PR77308).

Bootstrap & regress OK.

ChangeLog:
2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
        * config/arm/arm.c (arm_legitimate_index_p): Add comment.
        (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
--

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
         {
           HOST_WIDE_INT val = INTVAL (index);
 
+         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
           if (TARGET_LDRD)
             return val > -256 && val < 256;
           else
@@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
       if (code == CONST_INT)
         {
           HOST_WIDE_INT val = INTVAL (index);
-         /* ??? Can we assume ldrd for thumb2?  */
-         /* Thumb-2 ldrd only has reg+const addressing modes.  */
-         /* ldrd supports offsets of +-1020.
-            However the ldr fallback does not.  */
-         return val > -256 && val < 256 && (val & 3) == 0;
+         /* Thumb-2 ldrd only has reg+const addressing modes.
+            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
+         if (TARGET_LDRD)
+           return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
+         else
+           return IN_RANGE (val, -255, 4095 - 4);
         }
       else
         return 0;            

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2017-01-17 12:12     ` Wilco Dijkstra
@ 2017-02-02 14:45       ` Wilco Dijkstra
  2017-02-23 16:57         ` Wilco Dijkstra
  0 siblings, 1 reply; 12+ messages in thread
From: Wilco Dijkstra @ 2017-02-02 14:45 UTC (permalink / raw)
  To: GCC Patches, Ramana Radhakrishnan, Kyrylo Tkachov; +Cc: nd


    
ping


From: Wilco Dijkstra
Sent: 03 November 2016 12:20
To: GCC Patches
Cc: nd
Subject: [PATCH][ARM] Fix ldrd offsets
    
Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
without -255..4091.  This reduces the number of addressing instructions
when using DI mode operations (such as in PR77308).

Bootstrap & regress OK.

ChangeLog:
2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
        * config/arm/arm.c (arm_legitimate_index_p): Add comment.
        (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
--

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
         {
           HOST_WIDE_INT val = INTVAL (index);
 
+         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
           if (TARGET_LDRD)
             return val > -256 && val < 256;
           else
@@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
       if (code == CONST_INT)
         {
           HOST_WIDE_INT val = INTVAL (index);
-         /* ??? Can we assume ldrd for thumb2?  */
-         /* Thumb-2 ldrd only has reg+const addressing modes.  */
-         /* ldrd supports offsets of +-1020.
-            However the ldr fallback does not.  */
-         return val > -256 && val < 256 && (val & 3) == 0;
+         /* Thumb-2 ldrd only has reg+const addressing modes.
+            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
+         if (TARGET_LDRD)
+           return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
+         else
+           return IN_RANGE (val, -255, 4095 - 4);
         }
       else
         return 0;                

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2017-02-02 14:45       ` Wilco Dijkstra
@ 2017-02-23 16:57         ` Wilco Dijkstra
  0 siblings, 0 replies; 12+ messages in thread
From: Wilco Dijkstra @ 2017-02-23 16:57 UTC (permalink / raw)
  To: GCC Patches, Ramana Radhakrishnan, Kyrylo Tkachov; +Cc: nd


    
ping


From: Wilco Dijkstra
Sent: 03 November 2016 12:20
To: GCC Patches
Cc: nd
Subject: [PATCH][ARM] Fix ldrd offsets
    
Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
without -255..4091.  This reduces the number of addressing instructions
when using DI mode operations (such as in PR77308).

Bootstrap & regress OK.

ChangeLog:
2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
        * config/arm/arm.c (arm_legitimate_index_p): Add comment.
        (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
--

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
         {
           HOST_WIDE_INT val = INTVAL (index);
 
+         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
           if (TARGET_LDRD)
             return val > -256 && val < 256;
           else
@@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
       if (code == CONST_INT)
         {
           HOST_WIDE_INT val = INTVAL (index);
-         /* ??? Can we assume ldrd for thumb2?  */
-         /* Thumb-2 ldrd only has reg+const addressing modes.  */
-         /* ldrd supports offsets of +-1020.
-            However the ldr fallback does not.  */
-         return val > -256 && val < 256 && (val & 3) == 0;
+         /* Thumb-2 ldrd only has reg+const addressing modes.
+            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
+         if (TARGET_LDRD)
+           return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
+         else
+           return IN_RANGE (val, -255, 4095 - 4);
         }
       else
         return 0;                    

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2016-11-03 12:21 [PATCH][ARM] Fix ldrd offsets Wilco Dijkstra
  2016-11-08 14:08 ` Ramana Radhakrishnan
  2016-12-06 15:13 ` Wilco Dijkstra
@ 2017-04-20 16:07 ` Wilco Dijkstra
  2017-06-13 13:59   ` Wilco Dijkstra
  2 siblings, 1 reply; 12+ messages in thread
From: Wilco Dijkstra @ 2017-04-20 16:07 UTC (permalink / raw)
  To: GCC Patches, Kyrylo Tkachov; +Cc: nd, Richard Earnshaw


ping

From: Wilco Dijkstra
Sent: 03 November 2016 12:20
To: GCC Patches
Cc: nd
Subject: [PATCH][ARM] Fix ldrd offsets
    
Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
without -255..4091.  This reduces the number of addressing instructions
when using DI mode operations (such as in PR77308).

Bootstrap & regress OK.

ChangeLog:
2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
        * config/arm/arm.c (arm_legitimate_index_p): Add comment.
        (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
--

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
         {
           HOST_WIDE_INT val = INTVAL (index);
 
+         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
           if (TARGET_LDRD)
             return val > -256 && val < 256;
           else
@@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
       if (code == CONST_INT)
         {
           HOST_WIDE_INT val = INTVAL (index);
-         /* ??? Can we assume ldrd for thumb2?  */
-         /* Thumb-2 ldrd only has reg+const addressing modes.  */
-         /* ldrd supports offsets of +-1020.
-            However the ldr fallback does not.  */
-         return val > -256 && val < 256 && (val & 3) == 0;
+         /* Thumb-2 ldrd only has reg+const addressing modes.
+            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
+         if (TARGET_LDRD)
+           return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
+         else
+           return IN_RANGE (val, -255, 4095 - 4);
         }
       else
         return 0;    

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2017-04-20 16:07 ` Wilco Dijkstra
@ 2017-06-13 13:59   ` Wilco Dijkstra
  2017-06-27 15:39     ` Wilco Dijkstra
  0 siblings, 1 reply; 12+ messages in thread
From: Wilco Dijkstra @ 2017-06-13 13:59 UTC (permalink / raw)
  To: GCC Patches, Kyrylo Tkachov; +Cc: nd, Richard Earnshaw


    

ping

From: Wilco Dijkstra
Sent: 03 November 2016 12:20
To: GCC Patches
Cc: nd
Subject: [PATCH][ARM] Fix ldrd offsets
    
Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
without -255..4091.  This reduces the number of addressing instructions
when using DI mode operations (such as in PR77308).

Bootstrap & regress OK.

ChangeLog:
2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
        * config/arm/arm.c (arm_legitimate_index_p): Add comment.
        (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
--

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
         {
           HOST_WIDE_INT val = INTVAL (index);
 
+         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
           if (TARGET_LDRD)
             return val > -256 && val < 256;
           else
@@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
       if (code == CONST_INT)
         {
           HOST_WIDE_INT val = INTVAL (index);
-         /* ??? Can we assume ldrd for thumb2?  */
-         /* Thumb-2 ldrd only has reg+const addressing modes.  */
-         /* ldrd supports offsets of +-1020.
-            However the ldr fallback does not.  */
-         return val > -256 && val < 256 && (val & 3) == 0;
+         /* Thumb-2 ldrd only has reg+const addressing modes.
+            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
+         if (TARGET_LDRD)
+           return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
+         else
+           return IN_RANGE (val, -255, 4095 - 4);
         }
       else
         return 0;        

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2017-06-13 13:59   ` Wilco Dijkstra
@ 2017-06-27 15:39     ` Wilco Dijkstra
  2017-09-04 17:00       ` Kyrill Tkachov
  0 siblings, 1 reply; 12+ messages in thread
From: Wilco Dijkstra @ 2017-06-27 15:39 UTC (permalink / raw)
  To: GCC Patches, Kyrylo Tkachov; +Cc: nd, Richard Earnshaw

    

ping

From: Wilco Dijkstra
Sent: 03 November 2016 12:20
To: GCC Patches
Cc: nd
Subject: [PATCH][ARM] Fix ldrd offsets
    
Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
without -255..4091.  This reduces the number of addressing instructions
when using DI mode operations (such as in PR77308).

Bootstrap & regress OK.

ChangeLog:
2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>

    gcc/
        * config/arm/arm.c (arm_legitimate_index_p): Add comment.
        (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
--

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
         {
           HOST_WIDE_INT val = INTVAL (index);
 
+         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
           if (TARGET_LDRD)
             return val > -256 && val < 256;
           else
@@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
       if (code == CONST_INT)
         {
           HOST_WIDE_INT val = INTVAL (index);
-         /* ??? Can we assume ldrd for thumb2?  */
-         /* Thumb-2 ldrd only has reg+const addressing modes.  */
-         /* ldrd supports offsets of +-1020.
-            However the ldr fallback does not.  */
-         return val > -256 && val < 256 && (val & 3) == 0;
+         /* Thumb-2 ldrd only has reg+const addressing modes.
+            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
+            If vldr is selected it uses arm_coproc_mem_operand.  */
+         if (TARGET_LDRD)
+           return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
+         else
+           return IN_RANGE (val, -255, 4095 - 4);
         }
       else
         return 0;            

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH][ARM] Fix ldrd offsets
  2017-06-27 15:39     ` Wilco Dijkstra
@ 2017-09-04 17:00       ` Kyrill Tkachov
  0 siblings, 0 replies; 12+ messages in thread
From: Kyrill Tkachov @ 2017-09-04 17:00 UTC (permalink / raw)
  To: Wilco Dijkstra, GCC Patches; +Cc: nd, Richard Earnshaw


On 27/06/17 16:39, Wilco Dijkstra wrote:
>
>
> ping
>
> From: Wilco Dijkstra
> Sent: 03 November 2016 12:20
> To: GCC Patches
> Cc: nd
> Subject: [PATCH][ARM] Fix ldrd offsets
>
> Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020,
> without -255..4091.  This reduces the number of addressing instructions
> when using DI mode operations (such as in PR77308).
>
> Bootstrap & regress OK.
>
Ok.

Thanks,
Kyrill


> ChangeLog:
> 2015-11-03  Wilco Dijkstra  <wdijkstr@arm.com>
>
>     gcc/
>         * config/arm/arm.c (arm_legitimate_index_p): Add comment.
>         (thumb2_legitimate_index_p): Use correct range for DI/DF mode.
> --
>
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 
> 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584bde36ec86bb3fe 
> 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx 
> index, RTX_CODE outer,
>          {
>            HOST_WIDE_INT val = INTVAL (index);
>
> +         /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
> +            If vldr is selected it uses arm_coproc_mem_operand.  */
>            if (TARGET_LDRD)
>              return val > -256 && val < 256;
>            else
> @@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, 
> rtx index, int strict_p)
>        if (code == CONST_INT)
>          {
>            HOST_WIDE_INT val = INTVAL (index);
> -         /* ??? Can we assume ldrd for thumb2?  */
> -         /* Thumb-2 ldrd only has reg+const addressing modes.  */
> -         /* ldrd supports offsets of +-1020.
> -            However the ldr fallback does not.  */
> -         return val > -256 && val < 256 && (val & 3) == 0;
> +         /* Thumb-2 ldrd only has reg+const addressing modes.
> +            Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
> +            If vldr is selected it uses arm_coproc_mem_operand.  */
> +         if (TARGET_LDRD)
> +           return IN_RANGE (val, -1020, 1020) && (val & 3) == 0;
> +         else
> +           return IN_RANGE (val, -255, 4095 - 4);
>          }
>        else
>          return 0;

^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2017-09-04 17:00 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-03 12:21 [PATCH][ARM] Fix ldrd offsets Wilco Dijkstra
2016-11-08 14:08 ` Ramana Radhakrishnan
2016-11-11 10:59   ` Wilco Dijkstra
2016-12-06 15:13 ` Wilco Dijkstra
2016-12-14 16:41   ` Wilco Dijkstra
2017-01-17 12:12     ` Wilco Dijkstra
2017-02-02 14:45       ` Wilco Dijkstra
2017-02-23 16:57         ` Wilco Dijkstra
2017-04-20 16:07 ` Wilco Dijkstra
2017-06-13 13:59   ` Wilco Dijkstra
2017-06-27 15:39     ` Wilco Dijkstra
2017-09-04 17:00       ` Kyrill Tkachov

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