From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 102841 invoked by alias); 12 Jun 2017 10:50:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 102753 invoked by uid 89); 12 Jun 2017 10:50:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=0.5 X-HELO: EUR03-DB5-obe.outbound.protection.outlook.com Received: from mail-eopbgr40060.outbound.protection.outlook.com (HELO EUR03-DB5-obe.outbound.protection.outlook.com) (40.107.4.60) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 12 Jun 2017 10:50:33 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com (10.175.46.18) by AM4PR08MB2658.eurprd08.prod.outlook.com (10.171.190.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1157.12; Mon, 12 Jun 2017 10:50:34 +0000 Received: from AM5PR0802MB2610.eurprd08.prod.outlook.com ([fe80::55:95b4:a335:b34b]) by AM5PR0802MB2610.eurprd08.prod.outlook.com ([fe80::55:95b4:a335:b34b%17]) with mapi id 15.01.1157.017; Mon, 12 Jun 2017 10:50:34 +0000 From: Wilco Dijkstra To: GCC Patches CC: nd , James Greenhalgh Subject: [PATCH][AArch64] Change FP reassociation width Date: Mon, 12 Jun 2017 10:50:00 -0000 Message-ID: authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM4PR08MB2658;7:Rt20pIwpOndVRxAQz6pqDaC0uLtbfbLsda61rzzz+uoP27mcvPs2MPI2H3GGzEsPxOfSpoELrZaDLwsB5sa/GBUQf/ExSUENop2xzPAy3YsES2jgh2HmFtTDeNJRa4to/Obx0HE4/3C4frCFnKdfuo105yGqFyRppKewE5dKrb/nHraBfO+F9vEakUhxT8vpCo0wALjpP8lf8H0LmM88HP8jSao7UtWD03vj2HA4wsDkk9qymIBXTx0JCHVXgVNw+SOe1j0CboBQcTarq5B52QP/Z3snsX1Vr8KkpnpEf12YU9hiPCPAjjD0ltb207JKqrVTQ0hp07uV0dWOuWTdkQ== x-ms-traffictypediagnostic: AM4PR08MB2658: x-ms-office365-filtering-correlation-id: 5a597476-abb1-482f-709b-08d4b180da96 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081);SRVR:AM4PR08MB2658; nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(100000703101)(100105400095)(93006095)(93001095)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123564025)(20161123560025)(20161123555025)(20161123558100)(6072148)(100000704101)(100105200095)(100000705101)(100105500095);SRVR:AM4PR08MB2658;BCL:0;PCL:0;RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);SRVR:AM4PR08MB2658; x-forefront-prvs: 03361FCC43 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(39840400002)(39860400002)(39850400002)(39400400002)(39410400002)(39450400003)(54534003)(377424004)(74316002)(5660300001)(189998001)(4326008)(5250100002)(25786009)(33656002)(102836003)(110136004)(53936002)(38730400002)(7696004)(14454004)(478600001)(72206003)(2906002)(6506006)(55016002)(9686003)(99286003)(54906002)(6436002)(6916009)(7736002)(305945005)(3280700002)(3660700001)(54356999)(2900100001)(86362001)(50986999)(81166006)(8676002)(8936002);DIR:OUT;SFP:1101;SCL:1;SRVR:AM4PR08MB2658;H:AM5PR0802MB2610.eurprd08.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Jun 2017 10:50:34.5742 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR08MB2658 X-SW-Source: 2017-06/txt/msg00771.txt.bz2 Currently the FP reassociation width is set to 4 on AArch64. On recent GCCs this has become more aggressive in splitting expressions. This means many FMAs are split into FMUL and FADD. The reassociation increases regist= er pressure, in some benchmarks so much that inner loops start to spill. This results in larger, slower code. Benchmarking FP reassociation width= =3D1 showed a ~0.5% gain on SPECFP2006 and similar gains on other benchmarks, so change it to 1. Passes regress & bootstrap, OK for commit? ChangeLog: 2017-06-12 Wilco Dijkstra * gcc/config/aarch64/aarch64.c (generic_tuning): Set fp_reassoc_width to 1. (cortexa35_tunings): Likewise. (cortexa53_tunings): Likewise. (cortexa57_tunings): Likewise. (cortexa72_tunings): Likewise. (cortexa73_tunings): Likewise. -- diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 72a758642743025ac8974c8f7ad4c44c31a474d5..0998bf37b2abf399277d2f2a539= 295506085209f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -541,7 +541,7 @@ static const struct tune_params generic_tunings =3D 4, /* jump_align. */ 8, /* loop_align. */ 2, /* int_reassoc_width. */ - 4, /* fp_reassoc_width. */ + 1, /* fp_reassoc_width. */ 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ @@ -567,7 +567,7 @@ static const struct tune_params cortexa35_tunings =3D 8, /* jump_align. */ 8, /* loop_align. */ 2, /* int_reassoc_width. */ - 4, /* fp_reassoc_width. */ + 1, /* fp_reassoc_width. */ 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ @@ -593,7 +593,7 @@ static const struct tune_params cortexa53_tunings =3D 8, /* jump_align. */ 8, /* loop_align. */ 2, /* int_reassoc_width. */ - 4, /* fp_reassoc_width. */ + 1, /* fp_reassoc_width. */ 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ @@ -619,7 +619,7 @@ static const struct tune_params cortexa57_tunings =3D 8, /* jump_align. */ 8, /* loop_align. */ 2, /* int_reassoc_width. */ - 4, /* fp_reassoc_width. */ + 1, /* fp_reassoc_width. */ 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ @@ -645,7 +645,7 @@ static const struct tune_params cortexa72_tunings =3D 8, /* jump_align. */ 8, /* loop_align. */ 2, /* int_reassoc_width. */ - 4, /* fp_reassoc_width. */ + 1, /* fp_reassoc_width. */ 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ @@ -671,7 +671,7 @@ static const struct tune_params cortexa73_tunings =3D 8, /* jump_align. */ 8, /* loop_align. */ 2, /* int_reassoc_width. */ - 4, /* fp_reassoc_width. */ + 1, /* fp_reassoc_width. */ 1, /* vec_reassoc_width. */ 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */