From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18151 invoked by alias); 30 Jul 2019 20:51:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 17984 invoked by uid 89); 30 Jul 2019 20:51:39 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.1 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_2,GIT_PATCH_3,KAM_ASCII_DIVIDERS,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.1 spammy=H*Ad:U*ebotcazou, H*M:COM, hits X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com Received: from mail-oln040092064048.outbound.protection.outlook.com (HELO EUR01-DB5-obe.outbound.protection.outlook.com) (40.92.64.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 30 Jul 2019 20:51:37 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OyQaQ8/wSfhkT81/7UNKGzhd+3y2ctEnWvZDf4S36xTUMeVl3mhwxlVDeYuQ+QtNHJBIU+sUTAQwWF/0QqO5bFIeao7I6v1ws4s+Vor/RfVlKzwH1OD1TvvTBDyP8/6foJbdquPvAuSf8xs+re1BarH1pOkVxRhrZB95HuT5j4HQNLFbWOvHkq+X+9et7gHyHsIqojfrgPRF5suhBbUJncflmMyrK3BIpVThz8xbqdAFEBzAdHS0Gb3ZrTIr4fVj3Fnq+zbNkr0K975Ey2Ri9MIEXwst5L0G+iBqSEgKDURnkjy6AAutqKgqAzaQE4L8GCXKzzF6Z53AlzAg/GhkmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tZK5TgoCoNVsElob0UhZI2RTysWDFEfKqimOe8qB3h4=; b=HZo/TLtgI2WUwspcBP1DTe8XEP3LHRpADAsEjcfV0D5ZRNsAilNqlv9QYEmtrdbBICtjRjb9d4oKdG2XvcQuFEcXyYwm7AaXRHswxLvTR5gDvS5O3gM1x4LrMxsRGapAEnUOSA4S4ztCG4/TI2eH/ZGGhpvTWskvr7DKUIU8w6LRGxe91orLBEbVPO0iIosCwTL9UfUzxkCUsJPfC3TnPWdopENrtP/qgiNesfFGJfBVwKItSJ+9R9kDkEvtfGxLK4zw6jFwQimpyR5Ow0llQvmtVztyI05TVP3UoO7lRGLmCn/TN3Xwxmu8AryFZ4q2V0PDaA5URbr7a7oeWy8q8g== ARC-Authentication-Results: i=1; mx.microsoft.com 1;spf=none;dmarc=none;dkim=none;arc=none Received: from VE1EUR01FT056.eop-EUR01.prod.protection.outlook.com (10.152.2.57) by VE1EUR01HT091.eop-EUR01.prod.protection.outlook.com (10.152.3.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2115.10; Tue, 30 Jul 2019 20:51:34 +0000 Received: from AM6PR10MB2566.EURPRD10.PROD.OUTLOOK.COM (10.152.2.54) by VE1EUR01FT056.mail.protection.outlook.com (10.152.3.115) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2115.10 via Frontend Transport; Tue, 30 Jul 2019 20:51:34 +0000 Received: from AM6PR10MB2566.EURPRD10.PROD.OUTLOOK.COM ([fe80::c488:4d1b:6ada:37cc]) by AM6PR10MB2566.EURPRD10.PROD.OUTLOOK.COM ([fe80::c488:4d1b:6ada:37cc%3]) with mapi id 15.20.2136.010; Tue, 30 Jul 2019 20:51:34 +0000 From: Bernd Edlinger To: Richard Biener CC: "gcc-patches@gcc.gnu.org" , Richard Earnshaw , Ramana Radhakrishnan , Kyrill Tkachov , Eric Botcazou Subject: [PATCHv3] Fix not 8-byte aligned ldrd/strd on ARMv5 (PR 89544) Date: Tue, 30 Jul 2019 22:13:00 -0000 Message-ID: References: In-Reply-To: x-microsoft-original-message-id: <1cfebf90-6a73-d54f-deaf-270dc59b11d2@hotmail.de> Content-Type: multipart/mixed; boundary="_002_AM6PR10MB256664D731C3CC92F2FBEDC5E4DC0AM6PR10MB2566EURP_" MIME-Version: 1.0 X-SW-Source: 2019-07/txt/msg01832.txt.bz2 --_002_AM6PR10MB256664D731C3CC92F2FBEDC5E4DC0AM6PR10MB2566EURP_ Content-Type: text/plain; charset="Windows-1252" Content-ID: Content-Transfer-Encoding: quoted-printable Content-length: 3542 Hi Richard, it is already a while ago, but I had not found time to continue with this patch until now. I think I have now a better solution, which properly addresses your comments below. On 3/25/19 9:41 AM, Richard Biener wrote: > On Fri, 22 Mar 2019, Bernd Edlinger wrote: >=20 >> On 3/21/19 12:15 PM, Richard Biener wrote: >>> On Sun, 10 Mar 2019, Bernd Edlinger wrote: >>> Finally... >>> >>> Index: gcc/function.c >>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>> --- gcc/function.c (revision 269264) >>> +++ gcc/function.c (working copy) >>> @@ -2210,6 +2210,12 @@ use_register_for_decl (const_tree decl) >>> if (DECL_MODE (decl) =3D=3D BLKmode) >>> return false; >>> >>> + if (STRICT_ALIGNMENT && TREE_CODE (decl) =3D=3D PARM_DECL >>> + && DECL_INCOMING_RTL (decl) && MEM_P (DECL_INCOMING_RTL (decl)) >>> + && GET_MODE_ALIGNMENT (DECL_MODE (decl)) >>> + > MEM_ALIGN (DECL_INCOMING_RTL (decl))) >>> + return false; >>> + >>> /* If -ffloat-store specified, don't put explicit float variables >>> into registers. */ >>> /* ??? This should be checked after DECL_ARTIFICIAL, but tree-ssa >>> >>> I wonder if it is necessary to look at DECL_INCOMING_RTL here >>> and why such RTL may not exist? That is, iff DECL_INCOMING_RTL >>> doesn't exist then shouldn't we return false for safety reasons? >>> You are right, it is not possbile to return different results from use_register_for_decl before vs. after incoming RTL is assigned. That hits an assertion in set_rtl. This hunk is gone now, instead I changed assign_parm_setup_reg to use movmisalign optab and/or extract_bit_field if misaligned entry_parm is to be assigned in a register. I have no test coverage for the movmisalign optab though, so I rely on your code review for that part. >>> Similarly the very same issue should exist on x86_64 which is >>> !STRICT_ALIGNMENT, it's just the ABI seems to provide the appropriate >>> alignment on the caller side. So the STRICT_ALIGNMENT check is >>> a wrong one. >>> >> >> I may be plain wrong here, but I thought that !STRICT_ALIGNMENT targets >> just use MEM_ALIGN to select the right instructions. MEM_ALIGN >> is always 32-bit align on the DImode memory. The x86_64 vector instruct= ions >> would look at MEM_ALIGN and do the right thing, yes? >=20 > No, they need to use the movmisalign optab and end up with UNSPECs > for example. Ah, thanks, now I see. >> It seems to be the definition of STRICT_ALIGNMENT targets that all RTL >> instructions need to have MEM_ALIGN >=3D GET_MODE_ALIGNMENT, so the targ= et >> does not even have to look at MEM_ALIGN except in the mov_misalign_optab, >> right? >=20 > Yes, I think we never losened that. Note that RTL expansion has to > fix this up for them. Note that strictly speaking SLOW_UNALIGNED_ACCESS > specifies that x86 is strict-align wrt vector modes. >=20 Yes I agree, the code would be incorrect for x86 as well when the movmisali= gn_optab is not used. So I invoke the movmisalign optab if available and if not fall back to extract_bit_field. As in the assign_parm_setup_stack assign_parm_s= etup_reg assumes that data->promoted_mode !=3D data->nominal_mode does not happen wi= th misaligned stack slots. Attached is the v3 if my patch. Boot-strapped and reg-tested on x86_64-pc-linux-gnu and arm-linux-gnueabihf. Is it OK for trunk? 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