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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2023 10:20:47.1687 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de8eaddb-4db4-4189-7306-08dbd47ae394 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001A4.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB8886 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Ping=0A= =0A= ________________________________________=0A= From: Ezra.Sitorus@arm.com =0A= Sent: Friday, October 6, 2023 10:49 AM=0A= To: gcc-patches@gcc.gnu.org=0A= Cc: Richard Earnshaw; Kyrylo Tkachov=0A= Subject: [PATCH 1/3] [GCC] arm: vld1q_types_x2 ACLE intrinsics=0A= =0A= From: Ezra Sitorus =0A= =0A= This patch is part of a series of patches implementing the _xN variants of = the vld1q intrinsic for arm32.=0A= This patch adds the _x2 variants of the vld1q intrinsic. Tests use xN so th= at the latter variants (_x3, _x4) could be added.=0A= =0A= ACLE documents are at https://developer.arm.com/documentation/ihi0053/lates= t/=0A= ISA documents are at https://developer.arm.com/documentation/ddi0487/latest= /=0A= =0A= gcc/ChangeLog:=0A= * config/arm/arm_neon.h=0A= (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.=0A= (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.=0A= (vld1q_f16_x2, vld1q_f32_x2): New.=0A= (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.=0A= (vld1q_bf16_x2): New.=0A= * config/arm/arm_neon_builtins.def (vld1_x2): New entries.=0A= * config/arm/neon.md (vld1_x2): New.=0A= =0A= gcc/testsuite/ChangeLog:=0A= * gcc.target/arm/simd/vld1q_base_xN_1.c: Add new test.=0A= * gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new test.=0A= * gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new test.=0A= * gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new test.=0A= ---=0A= gcc/config/arm/arm_neon.h | 128 ++++++++++++++++++=0A= gcc/config/arm/arm_neon_builtins.def | 1 +=0A= gcc/config/arm/neon.md | 10 ++=0A= .../gcc.target/arm/simd/vld1q_base_xN_1.c | 67 +++++++++=0A= .../gcc.target/arm/simd/vld1q_bf16_xN_1.c | 13 ++=0A= .../gcc.target/arm/simd/vld1q_fp16_xN_1.c | 14 ++=0A= .../gcc.target/arm/simd/vld1q_p64_xN_1.c | 14 ++=0A= 7 files changed, 247 insertions(+)=0A= create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c=0A= create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c=0A= create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c=0A= create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c=0A= =0A= diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h=0A= index cdfdb44259a..3eb41c6bdc8 100644=0A= --- a/gcc/config/arm/arm_neon.h=0A= +++ b/gcc/config/arm/arm_neon.h=0A= @@ -10403,6 +10403,15 @@ vld1q_p64 (const poly64_t * __a)=0A= return (poly64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) = __a);=0A= }=0A= =0A= +__extension__ extern __inline poly64x2x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_p64_x2 (const poly64_t * __a)=0A= +{=0A= + union { poly64x2x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a= );=0A= + return __rv.__i;=0A= +}=0A= +=0A= #pragma GCC pop_options=0A= __extension__ extern __inline int8x16_t=0A= __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= @@ -10432,6 +10441,42 @@ vld1q_s64 (const int64_t * __a)=0A= return (int64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) _= _a);=0A= }=0A= =0A= +__extension__ extern __inline int8x16x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_s8_x2 (const int8_t * __a)=0A= +{=0A= + union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __= a);=0A= + return __rv.__i;=0A= +}=0A= +=0A= +__extension__ extern __inline int16x8x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_s16_x2 (const int16_t * __a)=0A= +{=0A= + union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a= );=0A= + return __rv.__i;=0A= +}=0A= +=0A= +__extension__ extern __inline int32x4x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_s32_x2 (const int32_t * __a)=0A= +{=0A= + union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a= );=0A= + return __rv.__i;=0A= +}=0A= +=0A= +__extension__ extern __inline int64x2x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_s64_x2 (const int64_t * __a)=0A= +{=0A= + union { int64x2x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a= );=0A= + return __rv.__i;=0A= +}=0A= +=0A= #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNA= TIVE)=0A= __extension__ extern __inline float16x8_t=0A= __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= @@ -10448,6 +10493,26 @@ vld1q_f32 (const float32_t * __a)=0A= return (float32x4_t)__builtin_neon_vld1v4sf ((const __builtin_neon_sf *)= __a);=0A= }=0A= =0A= +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNA= TIVE)=0A= +__extension__ extern __inline float16x8x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_f16_x2 (const float16_t * __a)=0A= +{=0A= + union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v8hf (__a);=0A= + return __rv.__i;=0A= +}=0A= +#endif=0A= +=0A= +__extension__ extern __inline float32x4x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_f32_x2 (const float32_t * __a)=0A= +{=0A= + union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v4sf ((const __builtin_neon_sf *) __a= );=0A= + return __rv.__i;=0A= +}=0A= +=0A= __extension__ extern __inline uint8x16_t=0A= __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= vld1q_u8 (const uint8_t * __a)=0A= @@ -10476,6 +10541,42 @@ vld1q_u64 (const uint64_t * __a)=0A= return (uint64x2_t)__builtin_neon_vld1v2di ((const __builtin_neon_di *) = __a);=0A= }=0A= =0A= +__extension__ extern __inline uint8x16x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_u8_x2 (const uint8_t * __a)=0A= +{=0A= + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __= a);=0A= + return __rv.__i;=0A= +}=0A= +=0A= +__extension__ extern __inline uint16x8x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_u16_x2 (const uint16_t * __a)=0A= +{=0A= + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a= );=0A= + return __rv.__i;=0A= +}=0A= +=0A= +__extension__ extern __inline uint32x4x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_u32_x2 (const uint32_t * __a)=0A= +{=0A= + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a= );=0A= + return __rv.__i;=0A= +}=0A= +=0A= +__extension__ extern __inline uint64x2x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_u64_x2 (const uint64_t * __a)=0A= +{=0A= + union { uint64x2x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a= );=0A= + return __rv.__i;=0A= +}=0A= +=0A= __extension__ extern __inline poly8x16_t=0A= __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= vld1q_p8 (const poly8_t * __a)=0A= @@ -10490,6 +10591,24 @@ vld1q_p16 (const poly16_t * __a)=0A= return (poly16x8_t)__builtin_neon_vld1v8hi ((const __builtin_neon_hi *) = __a);=0A= }=0A= =0A= +__extension__ extern __inline poly8x16x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_p8_x2 (const poly8_t * __a)=0A= +{=0A= + union { poly8x16x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __= a);=0A= + return __rv.__i;=0A= +}=0A= +=0A= +__extension__ extern __inline poly16x8x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_p16_x2 (const poly16_t * __a)=0A= +{=0A= + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a= );=0A= + return __rv.__i;=0A= +}=0A= +=0A= __extension__ extern __inline int8x8_t=0A= __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= vld1_lane_s8 (const int8_t * __a, int8x8_t __b, const int __c)=0A= @@ -19782,6 +19901,15 @@ vld1q_bf16 (const bfloat16_t * __ptr)=0A= return __builtin_neon_vld1v8bf (__ptr);=0A= }=0A= =0A= +__extension__ extern __inline bfloat16x8x2_t=0A= +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= +vld1q_bf16_x2 (const bfloat16_t * __ptr)=0A= +{=0A= + union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv;=0A= + __rv.__o =3D __builtin_neon_vld1_x2v8bf ((const __builtin_neon_bf *) __p= tr);=0A= + return __rv.__i;=0A= +}=0A= +=0A= __extension__ extern __inline bfloat16x4x2_t=0A= __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))=0A= vld2_bf16 (bfloat16_t const * __ptr)=0A= diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon= _builtins.def=0A= index 94b15238123..5fadd255c18 100644=0A= --- a/gcc/config/arm/arm_neon_builtins.def=0A= +++ b/gcc/config/arm/arm_neon_builtins.def=0A= @@ -298,6 +298,7 @@ VAR1 (TERNOP, vtbx1, v8qi)=0A= VAR1 (TERNOP, vtbx2, v8qi)=0A= VAR1 (TERNOP, vtbx3, v8qi)=0A= VAR1 (TERNOP, vtbx4, v8qi)=0A= +VAR7 (LOAD1, vld1_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)=0A= VAR13 (LOAD1, vld1,=0A= v8qi, v4hi, v4hf, v2si, v2sf, v16qi, v8hi, v8hf, v4si, v4sf, v2di,= =0A= v4bf, v8bf)=0A= diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md=0A= index d213369ffc3..55049ea549f 100644=0A= --- a/gcc/config/arm/neon.md=0A= +++ b/gcc/config/arm/neon.md=0A= @@ -4957,6 +4957,16 @@ if (BYTES_BIG_ENDIAN)=0A= [(set_attr "type" "neon_load1_1reg")]=0A= )=0A= =0A= +(define_insn "neon_vld1_x2"=0A= + [(set (match_operand:OI 0 "s_register_operand" "=3Dw")=0A= + (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")=0A= + (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]=0A= + UNSPEC_VLD1))]=0A= + "TARGET_NEON"=0A= + "vld1.\t%h0, %A1"=0A= + [(set_attr "type" "neon_load1_2reg")]=0A= +)=0A= +=0A= ;; The lane numbers in the RTL are in GCC lane order, having been flipped= =0A= ;; in arm_expand_neon_args. The lane numbers are restored to architectural= =0A= ;; lane order here.=0A= diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c b/gcc/test= suite/gcc.target/arm/simd/vld1q_base_xN_1.c=0A= new file mode 100644=0A= index 00000000000..1d31777afdf=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c=0A= @@ -0,0 +1,67 @@=0A= +/* { dg-do assemble } */=0A= +/* { dg-require-effective-target arm_neon_ok } */=0A= +/* { dg-options "-save-temps -O2" } */=0A= +/* { dg-add-options arm_neon } */=0A= +=0A= +#include "arm_neon.h"=0A= +=0A= +uint8x16x2_t test_vld1q_u8_x2 (uint8_t * a)=0A= +{=0A= + return vld1q_u8_x2 (a);=0A= +}=0A= +=0A= +uint16x8x2_t test_vld1q_u16_x2 (uint16_t * a)=0A= +{=0A= + return vld1q_u16_x2 (a);=0A= +}=0A= +=0A= +uint32x4x2_t test_vld1q_u32_x2 (uint32_t * a)=0A= +{=0A= + return vld1q_u32_x2 (a);=0A= +}=0A= +=0A= +uint64x2x2_t test_vld1q_u64_x2 (uint64_t * a)=0A= +{=0A= + return vld1q_u64_x2 (a);=0A= +}=0A= +=0A= +int8x16x2_t test_vld1q_s8_x2 (int8_t * a)=0A= +{=0A= + return vld1q_s8_x2 (a);=0A= +}=0A= +=0A= +int16x8x2_t test_vld1q_s16_x2 (int16_t * a)=0A= +{=0A= + return vld1q_s16_x2 (a);=0A= +}=0A= +=0A= +int32x4x2_t test_vld1q_s32_x2 (int32_t * a)=0A= +{=0A= + return vld1q_s32_x2 (a);=0A= +}=0A= +=0A= +int64x2x2_t test_vld1q_s64_x2 (int64_t * a)=0A= +{=0A= + return vld1q_s64_x2 (a);=0A= +}=0A= +=0A= +float32x4x2_t test_vld1q_f32_x2 (float32_t * a)=0A= +{=0A= + return vld1q_f32_x2 (a);=0A= +}=0A= +=0A= +poly8x16x2_t test_vld1q_p8_x2 (poly8_t * a)=0A= +{=0A= + return vld1q_p8_x2 (a);=0A= +}=0A= +=0A= +poly16x8x2_t test_vld1q_p16_x2 (poly16_t * a)=0A= +{=0A= + return vld1q_p16_x2 (a);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9= ]+\]\n} 3 } } */=0A= +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-= 9]+\]\n} 3 } } */=0A= +/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-= 9]+\]\n} 3 } } */=0A= +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-= 9]+:64\]\n} 2 } } */=0A= +=0A= diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c b/gcc/test= suite/gcc.target/arm/simd/vld1q_bf16_xN_1.c=0A= new file mode 100644=0A= index 00000000000..5f6fc98640e=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c=0A= @@ -0,0 +1,13 @@=0A= +/* { dg-do assemble } */=0A= +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */=0A= +/* { dg-options "-save-temps -O2" } */=0A= +/* { dg-add-options arm_v8_2a_bf16_neon } */=0A= +=0A= +#include "arm_neon.h"=0A= +=0A= +bfloat16x8x2_t test_vld1q_bf16_x2 (bfloat16_t * a)=0A= +{=0A= + return vld1q_bf16_x2 (a);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-= 9]+\]\n} 1 } } */=0A= diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c b/gcc/test= suite/gcc.target/arm/simd/vld1q_fp16_xN_1.c=0A= new file mode 100644=0A= index 00000000000..aecf491a4de=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c=0A= @@ -0,0 +1,14 @@=0A= +/* { dg-do assemble } */=0A= +/* { dg-require-effective-target arm_neon_fp16_ok } */=0A= +/* { dg-options "-save-temps -O2" } */=0A= +/* { dg-add-options arm_neon_fp16 } */=0A= +=0A= +#include "arm_neon.h"=0A= +=0A= +float16x8x2_t test_vld1q_f16_x2 (float16_t * a)=0A= +{=0A= + return vld1q_f16_x2 (a);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-= 9]+\]\n} 1 } } */=0A= +=0A= diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c b/gcc/tests= uite/gcc.target/arm/simd/vld1q_p64_xN_1.c=0A= new file mode 100644=0A= index 00000000000..04ceb5e4a24=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c=0A= @@ -0,0 +1,14 @@=0A= +/* { dg-do assemble } */=0A= +/* { dg-require-effective-target arm_crypto_ok } */=0A= +/* { dg-options "-save-temps -O2" } */=0A= +/* { dg-add-options arm_crypto } */=0A= +=0A= +#include "arm_neon.h"=0A= +=0A= +poly64x2x2_t test_vld1q_p64_x2 (poly64_t * a)=0A= +{=0A= + return vld1q_p64_x2 (a);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-= 9]+:64\]\n} 1 } } */=0A= +=0A= --=0A= 2.25.1=0A= =0A=