From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR02-AM5-obe.outbound.protection.outlook.com (mail-eopbgr00049.outbound.protection.outlook.com [40.107.0.49]) by sourceware.org (Postfix) with ESMTPS id D7735385AC3B for ; Wed, 5 Oct 2022 12:30:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D7735385AC3B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=bPq7JWZJQ/uAlQwoYwjrBeFY4CF3z2JMbwWyeduqXVYCxGWIYHbe1dOno7f4/axs1hhnrYBhpVpW+T+g9vyBs10cypdLdG0GYr/cPyrksX81bx8m1uCVS3x1Z8xyAGQbTmpoX3kdKqpaOZbQh8Gk3p6lklLtTEFrTAj0+E9fIUZ0fNyv9tGn5JLZpONCuquP87Bm+l9+5ihVoDic3jFYU3rjTHMN9bqXrMz4xHvqa9OvPA42oN/isa97xH18KHhgyMY2Xc+32eg7XbrlkcFTn0OtRq5VOty/Wh6zuoTcGOsRQvg45QX/s239hqkeQI/1pjOtODb6NmmLf/lhR9ZN4A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ToBIC23sszQ8REzsc6RDvLb+IO0gEOT3XheL4dMkAyo=; b=YGxo328kL3cbAtwiISva7IEpsewtbfIgbP2QWviBpfMGhbIv4gmZQnyPHQHknllJ46vSZ1t+NcPihhQzfkavVLgCAnlfhnvzfS7vDzf9OxFJECn8k687GP4weByf9dio34NRrdpMMiHHFH1KmRuLdnscAX994LCr7afusDiwocFlyOgPSdLk7NoqO0kbz9hRO8TLwoOqPwGqD3H+K158S09zu9uiJl8eLnGNKNGR/LwNmR2JHSprZtD9ZYtYUDQmLbVvM7+HslCdXo06+gfeRqFHHOXdITz/nAYDWJ9iWuJLdt0Upd6jNZJ9x3hqH5hkZu0Ms5P6R6J3bmVNVOErrw== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ToBIC23sszQ8REzsc6RDvLb+IO0gEOT3XheL4dMkAyo=; b=HakRF8+xCGXtokoLmtWMGYLFu48n78HU2OCkHzDsOylfIEF7HH9j5ftFOWXw0FSERvGwBM5Ith96vcaR5o2Udy6gUtQILyH1uKcGgDOriCJZYTVk8piDXWYw2NZiPIrkTW0H3ZsXygEneDkP5ZO8QFOr01Q+/KJVT6aL2sMWRBk= Received: from AS9PR06CA0769.eurprd06.prod.outlook.com (2603:10a6:20b:484::24) by DB9PR08MB7534.eurprd08.prod.outlook.com (2603:10a6:10:302::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.19; Wed, 5 Oct 2022 12:30:31 +0000 Received: from AM7EUR03FT005.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:484:cafe::62) by AS9PR06CA0769.outlook.office365.com (2603:10a6:20b:484::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.24 via Frontend Transport; Wed, 5 Oct 2022 12:30:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT005.mail.protection.outlook.com (100.127.140.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Wed, 5 Oct 2022 12:30:31 +0000 Received: ("Tessian outbound 99ee3885c6d5:v128"); Wed, 05 Oct 2022 12:30:30 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 56f421bbee3b6f2b X-CR-MTA-TID: 64aa7808 Received: from 6cc8442959ee.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 35FA5EB6-F8C9-4584-96E6-40D82AF3FEDB.1; Wed, 05 Oct 2022 12:30:24 +0000 Received: from EUR04-DB3-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 6cc8442959ee.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Wed, 05 Oct 2022 12:30:24 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ezzw2ZMG88bmCScRBJc0/vbue87KhLKgA28NBdHFnPmZeNxLqED8DtFh6a+CCZxKCCeMsy8ZFxOwvIwxgbpsM3eUL/v5FSfmDN87Mg5I0+VJNjFFkf1cstD/mez3GJFtCdbobTpUhJa4q8I/c1+bY9LRWyqxLzxo+RyTLN/H899KpdZvLBD7GHiFnngtOviL42vO8y+JcnUijhVPBLxCKlCSk66pMFQsgl2puWYz9WJgVC7LoPhfy2HcUSyqPam2rKoh7xFSGW8ccFmxtoe9AO/shFx6G/YPkp20dqeLNho2bg/SsVX61Lt+M8g/GAkXniC+nWX6Kx+54Zgg0yIiAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ToBIC23sszQ8REzsc6RDvLb+IO0gEOT3XheL4dMkAyo=; b=Bbyf2MOdY7hYIODOMm8MTqMIdxM4Bbsrhw2FkrKpuB+cZjeBAv6TK5i8IRdv+nEpDqSl4Wms3pEkZfUXhSKyQx8LmTK0x6eQLo0yMB6PaCTY2sxi8hgoGko+lwn8txnspenjkJKHwbcZJL9Ryqa7juJ7rSIjyQ5n19Gp8A4jAwiBVfee9Rm0XrqL0g7ZCt99gy4BaiG3H1biEluYWB7WZYk+Ih9kw/i9zbkKBQ/OAmJCI9qRgjlHPbQcOsFmyvNwn4aJAf7A1vjWo0zzl7lKZOoO58097ANrd2/P2waIuIBLgrGOVsxdp4AiSXOtOaWjJ0mYdCuWggbJfxXUiHpn6Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ToBIC23sszQ8REzsc6RDvLb+IO0gEOT3XheL4dMkAyo=; b=HakRF8+xCGXtokoLmtWMGYLFu48n78HU2OCkHzDsOylfIEF7HH9j5ftFOWXw0FSERvGwBM5Ith96vcaR5o2Udy6gUtQILyH1uKcGgDOriCJZYTVk8piDXWYw2NZiPIrkTW0H3ZsXygEneDkP5ZO8QFOr01Q+/KJVT6aL2sMWRBk= Received: from AS4PR08MB7901.eurprd08.prod.outlook.com (2603:10a6:20b:51c::16) by AS2PR08MB9570.eurprd08.prod.outlook.com (2603:10a6:20b:60a::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.24; Wed, 5 Oct 2022 12:30:22 +0000 Received: from AS4PR08MB7901.eurprd08.prod.outlook.com ([fe80::4d64:ef01:4d4c:6ba1]) by AS4PR08MB7901.eurprd08.prod.outlook.com ([fe80::4d64:ef01:4d4c:6ba1%8]) with mapi id 15.20.5676.032; Wed, 5 Oct 2022 12:30:22 +0000 From: Wilco Dijkstra To: GCC Patches CC: Richard Sandiford , Kyrylo Tkachov Subject: [PATCH][AArch64] Improve bit tests [PR105773] Thread-Topic: [PATCH][AArch64] Improve bit tests [PR105773] Thread-Index: AQHY2LXhPGQzp4WWbkOKTP58dpaxFQ== Date: Wed, 5 Oct 2022 12:30:22 +0000 Message-ID: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: AS4PR08MB7901:EE_|AS2PR08MB9570:EE_|AM7EUR03FT005:EE_|DB9PR08MB7534:EE_ X-MS-Office365-Filtering-Correlation-Id: 93c0c0f9-f871-48b3-49c9-08daa6cd6496 x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: /QfsCJTg6YC3+mGO8VDeUogrNcXcRKRLQLRkvjmR6FRXmjR55PZIYssCBSnyadVY3FZYZGpYL67Nd16yFOwaP5pvMlfrZ9kYt4t0Qk/ShAS4ozIMLA5tKn7OC71K09kC5eZBmabtLHgse/wfy3866p0FevzZE4JYY/odJV8vL39mf4IAj90Ewoh9Uq262LIL1yYgDOkvYcl9/A2rnyI9AfTWyOms1ejHmn/Rcqh9xxqr26JgcNc5EGO1gl17R4V7R8g/5MxAWXhXBBLWt0BOnXPMm3HheqzrzkyIK5S1XpoqY9Rjxwuis5hZU5tuy8MKRecSisGlMf9iGHaH5udxSJq5HdB5FroY2qbEX2IdPOqPkM0ga3MxWRfw5HnkCUKHepdhzXaanf3qwFy2LpKBadlwJoR9hBQjxchXVZyHpdMwvLkRxM+zET6BIGCMYgmVq1MlALAUhYuCQZImg8DGa0emZLIUUcHnqKpVnFgFehRCEfAkqqTFi7s3HCfbYRNA+o9pRR350h/5mtGU5haH5P4epgkmj0GC6qsYicXh6m8ka7maaLll6DFom17W+3RZpLRGeOnp/x76Kl/etXOS8+QLnISH8Gp/QxYe6kHK24EgSJ1VG07VYNNMz+Qn4kEBHBMvxwWlOLQM5Dk1uwuW6Vol1eePr5wFWo5oFfVGAl8uAOC5CavxnscbdWzeT3k2dS1REmXQMTavNOGnG8MMN4MMjjm49PB5HWOGR/QHIbr2YGll3jeyBNsVczrPKnO/2G4mtcMtNj+fDPtL/e0FhtT2SL/FHxiWZpMCrlXWZm6wZV6F8QJJjcyH7np/n9ak+onlFh4bYuLOTAYH4UYmQA== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AS4PR08MB7901.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(346002)(396003)(366004)(39860400002)(451199015)(38070700005)(6916009)(316002)(54906003)(71200400001)(478600001)(84970400001)(8936002)(38100700002)(7696005)(66556008)(122000001)(76116006)(66476007)(8676002)(66946007)(86362001)(91956017)(64756008)(66446008)(4326008)(41300700001)(9686003)(52536014)(33656002)(26005)(2906002)(5660300002)(6506007)(186003)(55016003);DIR:OUT;SFP:1101; Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9570 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: cf01ff92-3512-45b5-c46c-08daa6cd5f3f X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: b7y8UX8Y3G/9m3urCkgkKbO4x+a/h1YnAPDE+vebqM1EJ1jIonF4XYtIZiWnl8Ws7vJkDL3WYflcQaH+yO2fW2aUoNC6uZrIima+anxto2OIYLsCtRGQsUWgeE8e4OpNFI6KUxXFXEL2az4EvHbjJHH0bxpA4Gmz7Bjzc64RdLKvq3ERaWHVdS0dG40IqK7wyQ/hF2sTGcjf2Dr9Q0RJWibl2LYHk2D48xfGzyT9j+nGBuZlN9nmXvkzxFNHR2ny0tV9LaPA59MCTiScb3RsE3Wsb5aO4EQ3WDsNAN0FMkKj3t+EZxx3WO7x6pHvKYv9cMLFpuKiWF5CCQOHa8SwhgwBbsgyAkHEEI6gJTrncQ4ItHQpZAJYEqJ7hMk1ZSYYi78AKJUcNb+qHxVGz58jzb9sAw8S/5maAVWcd0Vk8BOWScDyl52hrjb+Pg7gzGCkSgZZw2NuIitEMv10+X4cdqvKw9TZwUg/AGxhPSlt8Q3gMutNQj2pCqs/CgK0V1Q8/YTGulFNKPQitKrvGphlFnj4WSgSRipS9q4aiXcAG+Qo3Wxx8kL8CkM/gOrMWDWAM8e/PTL8Q6Vzl397IMVxfSBxl2k00Yr74sbCyII5O98qSJQ7NHCGXWpQYMRJXBL4O9Za4fCDEeC5sK7Q9bfUj/KtYiO8+hVSZRnqelhKh0Y2jl4DPhixQxQ4o0iuUE9uOF1/fwPLY0plsC059gOi1PIxIvYVR0y5KpsUi8B4+2dpAlAVT0u6kwhrfgosmn8dM7Q9oYwYyjbgY0PlkMgxDGUReTfU6R4/aB4AoTmPUI7GrqzQ+2tWmzafCsLE+eBsytoEcxsuD6Y2IEXVJ+YNVw== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(39860400002)(376002)(136003)(451199015)(46966006)(36840700001)(40470700004)(356005)(82740400003)(70206006)(8936002)(316002)(70586007)(33656002)(82310400005)(6506007)(9686003)(4326008)(26005)(52536014)(86362001)(8676002)(81166007)(84970400001)(54906003)(6916009)(55016003)(40480700001)(41300700001)(478600001)(7696005)(186003)(36860700001)(40460700003)(47076005)(336012)(5660300002)(2906002);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2022 12:30:31.1642 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93c0c0f9-f871-48b3-49c9-08daa6cd6496 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7534 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: =0A= Since AArch64 sets all flags on logical operations, comparisons with zero= =0A= can be combined into an AND even if the condition is LE or GT.=0A= =0A= Passes regress, OK for commit?=0A= =0A= gcc:=0A= PR target/105773=0A= * config/aarch64/aarch64.cc (aarch64_select_cc_mode): Allow=0A= GT/LE for merging compare with zero into AND.=0A= (aarch64_get_condition_code_1): Support GT and LE in CC_NZmode.=0A= =0A= gcc/testsuite:=0A= PR target/105773=0A= * gcc.target/aarch64/ands_2.c: Test for ANDS.=0A= * gcc.target/aarch64/bics_2.c: Test for BICS.=0A= * gcc.target/aarch64/tst_2.c: Test for TST.=0A= * gcc.target/aarch64/tst_imm_split_1.c: Fix test.=0A= =0A= ---=0A= =0A= diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc= =0A= index 1601d11710cb6132c80a77bb4fe2f8429519aa5a..00876b08d8fbb1329a37a0ea73d= 3abf09d28b829 100644=0A= --- a/gcc/config/aarch64/aarch64.cc=0A= +++ b/gcc/config/aarch64/aarch64.cc=0A= @@ -11323,7 +11323,8 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y= )=0A= =0A= if ((mode_x =3D=3D SImode || mode_x =3D=3D DImode)=0A= && y =3D=3D const0_rtx=0A= - && (code =3D=3D EQ || code =3D=3D NE || code =3D=3D LT || code =3D= =3D GE)=0A= + && (code =3D=3D EQ || code =3D=3D NE || code =3D=3D LT || code =3D= =3D GE=0A= + || (code_x =3D=3D AND && (code =3D=3D GT || code =3D=3D LE)))=0A= && (code_x =3D=3D PLUS || code_x =3D=3D MINUS || code_x =3D=3D AND= =0A= || code_x =3D=3D NEG=0A= || (code_x =3D=3D ZERO_EXTRACT && CONST_INT_P (XEXP (x, 1))=0A= @@ -11471,6 +11472,8 @@ aarch64_get_condition_code_1 (machine_mode mode, en= um rtx_code comp_code)=0A= case EQ: return AARCH64_EQ;=0A= case GE: return AARCH64_PL;=0A= case LT: return AARCH64_MI;=0A= + case GT: return AARCH64_GT;=0A= + case LE: return AARCH64_LE;=0A= default: return -1;=0A= }=0A= break;=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/ands_2.c b/gcc/testsuite/gcc.= target/aarch64/ands_2.c=0A= index b061b1dfc59c1847cb799a1e49f8e5fc53bf2f14..c8763f234c5f7d19ef9c222756a= b5e8a6eaae6fe 100644=0A= --- a/gcc/testsuite/gcc.target/aarch64/ands_2.c=0A= +++ b/gcc/testsuite/gcc.target/aarch64/ands_2.c=0A= @@ -8,8 +8,7 @@ ands_si_test1 (int a, int b, int c)=0A= {=0A= int d =3D a & b;=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]= +" } } */=0A= - /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" }= } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -21,12 +20,11 @@ ands_si_test2 (int a, int b, int c)=0A= {=0A= int d =3D a & 0x99999999;=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986= 919" } } */=0A= - /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" = } } */=0A= - if (d <=3D 0)=0A= - return a + c;=0A= - else=0A= + /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919"= } } */=0A= + if (d > 0)=0A= return b + d + c;=0A= + else=0A= + return a + c;=0A= }=0A= =0A= int=0A= @@ -34,8 +32,7 @@ ands_si_test3 (int a, int b, int c)=0A= {=0A= int d =3D a & (b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]= +, lsl 3" } } */=0A= - /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, ls= l 3" } } */=0A= + /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, l= sl 3" } } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -49,8 +46,7 @@ ands_di_test1 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & b;=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]= +" } } */=0A= - /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" }= } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -62,12 +58,11 @@ ands_di_test2 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & 0xaaaaaaaaaaaaaaaall;=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, -6148914= 691236517206" } } */=0A= - /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -614891469123= 6517206" } } */=0A= - if (d <=3D 0)=0A= - return a + c;=0A= - else=0A= + /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, -61489146912= 36517206" } } */=0A= + if (d > 0)=0A= return b + d + c;=0A= + else=0A= + return a + c;=0A= }=0A= =0A= s64=0A= @@ -75,8 +70,7 @@ ands_di_test3 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & (b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]= +, lsl 3" } } */=0A= - /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, ls= l 3" } } */=0A= + /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, l= sl 3" } } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/bics_2.c b/gcc/testsuite/gcc.= target/aarch64/bics_2.c=0A= index 9ccae368c1276618bad691c78fb621a9c82794b7..c1f7e87a6121f7b067b7b37b149= da64aa63ebd1a 100644=0A= --- a/gcc/testsuite/gcc.target/aarch64/bics_2.c=0A= +++ b/gcc/testsuite/gcc.target/aarch64/bics_2.c=0A= @@ -8,8 +8,7 @@ bics_si_test1 (int a, int b, int c)=0A= {=0A= int d =3D a & ~b;=0A= =0A= - /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]= +" } } */=0A= - /* { dg-final { scan-assembler-times "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" }= } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -21,12 +20,11 @@ bics_si_test2 (int a, int b, int c)=0A= {=0A= int d =3D a & ~(b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]= +, lsl 3" } } */=0A= - /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, ls= l 3" } } */=0A= - if (d <=3D 0)=0A= - return a + c;=0A= - else=0A= + /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, l= sl 3" } } */=0A= + if (d > 0)=0A= return b + d + c;=0A= + else=0A= + return a + c;=0A= }=0A= =0A= typedef long long s64;=0A= @@ -36,8 +34,7 @@ bics_di_test1 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & ~b;=0A= =0A= - /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]= +" } } */=0A= - /* { dg-final { scan-assembler-times "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" }= } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -49,12 +46,11 @@ bics_di_test2 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & ~(b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]= +, lsl 3" } } */=0A= - /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, ls= l 3" } } */=0A= - if (d <=3D 0)=0A= - return a + c;=0A= - else=0A= + /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, l= sl 3" } } */=0A= + if (d > 0)=0A= return b + d + c;=0A= + else=0A= + return a + c;=0A= }=0A= =0A= int=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/tst_2.c b/gcc/testsuite/gcc.t= arget/aarch64/tst_2.c=0A= index c8b28fc5620a9140fee29c4455294af708642d69..3c9bdfd05c4a19e83150f84f454= c3e875c7757d1 100644=0A= --- a/gcc/testsuite/gcc.target/aarch64/tst_2.c=0A= +++ b/gcc/testsuite/gcc.target/aarch64/tst_2.c=0A= @@ -8,8 +8,7 @@ tst_si_test1 (int a, int b, int c)=0A= {=0A= int d =3D a & b;=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+= " } } */=0A= - /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+" } } */=0A= if (d <=3D 0)=0A= return 12;=0A= else=0A= @@ -21,12 +20,11 @@ tst_si_test2 (int a, int b, int c)=0A= {=0A= int d =3D a & 0x99999999;=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, -17179869= 19" } } */=0A= - /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" = } } */=0A= - if (d <=3D 0)=0A= - return 12;=0A= - else=0A= + /* { dg-final { scan-assembler "tst\tw\[0-9\]+, -1717986919" } } */=0A= + if (d > 0)=0A= return 18;=0A= + else=0A= + return 12;=0A= }=0A= =0A= int=0A= @@ -34,8 +32,7 @@ tst_si_test3 (int a, int b, int c)=0A= {=0A= int d =3D a & (b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+= , lsl 3" } } */=0A= - /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, ls= l 3" } } */=0A= + /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */= =0A= if (d <=3D 0)=0A= return 12;=0A= else=0A= @@ -49,8 +46,7 @@ tst_di_test1 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & b;=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+= " } } */=0A= - /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+" } } */=0A= if (d <=3D 0)=0A= return 12;=0A= else=0A= @@ -62,8 +58,7 @@ tst_di_test2 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & 0xaaaaaaaaaaaaaaaall;=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, -61489146= 91236517206" } } */=0A= - /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -614891469123= 6517206" } } */=0A= + /* { dg-final { scan-assembler "tst\tx\[0-9\]+, -6148914691236517206" } = } */=0A= if (d <=3D 0)=0A= return 12;=0A= else=0A= @@ -75,12 +70,11 @@ tst_di_test3 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & (b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+= , lsl 3" } } */=0A= - /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, ls= l 3" } } */=0A= - if (d <=3D 0)=0A= - return 12;=0A= - else=0A= + /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */= =0A= + if (d > 0)=0A= return 18;=0A= + else=0A= + return 12;=0A= }=0A= =0A= int=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c b/gcc/tests= uite/gcc.target/aarch64/tst_imm_split_1.c=0A= index 33a2c0f45afadb8fc9488f847f296ec0e690c049..e456e823593fbe507a8a67b5115= a45712e40f80e 100644=0A= --- a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c=0A= +++ b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c=0A= @@ -14,5 +14,4 @@ g (unsigned char *p)=0A= }=0A= =0A= /* { dg-final { scan-assembler-not "and\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+.*= " } } */=0A= -/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" } } = */=0A= -/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+, lsr = 4" } } */=0A= +/* { dg-final { scan-assembler-times "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+= " 2 } } */=0A= =0A=