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Thu, 20 Oct 2022 12:23:11 +0000 From: Wilco Dijkstra To: Richard Sandiford CC: Wilco Dijkstra via Gcc-patches Subject: Re: [PATCH][AArch64] Improve immediate expansion [PR106583] Thread-Topic: [PATCH][AArch64] Improve immediate expansion [PR106583] Thread-Index: AQHY2A60YLzBQMfh40K/8+uaM+WmL63/fNejgAIgoBGAAVDLSYAABmEYgAATQ+2AB9iuA4ALD4HdgAEtY2OAAC7UEg== Date: Thu, 20 Oct 2022 12:23:11 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: AS4PR08MB7901:EE_|AS4PR08MB8165:EE_|VI1EUR03FT021:EE_|DB9PR08MB6524:EE_ X-MS-Office365-Filtering-Correlation-Id: b5ae43c9-3a58-4554-875d-08dab295e3a4 x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: xKrGnu4xi8L3SgBYWKWgg/yEglSdbZbzoHfoTtJ7DrNKdiYtVLsHQCu8RUY5xK0oIrAQD2tnsOETXzyUIw/FETlGBXpOTxeDeTlarxzqtvynjTJuyG0gpMjn1aVHie/HuwBWMSPdPq/WkyqtGqlY8WJx83m8CMmZSff5hvx5+NDRvJyxs7ib5/8EZsggAtHxLWwgcxpHDgK3h/UprZQh5d/lJAkRLk36ukWmXZrGG6CfIR5iQ0cVley+bAhTslPunV4ipdQXWsrpQzo5jb+expv1OI5yz5etpQ5UcMXdP51d/Gqz8QXGmsLOJ3MoNlda2UkbA1tm0BMc5g/ODFXEDPCwn1mUy98fgOVIK01ppopdzOmkBsEh30niNmThE0ZAq3Lsj0Szp8ixyTTNlHoQ6CmVKi7sIkH6sEc9tyR/1T714VN95f1D1bB+5z/ECPYJfZBxV5gVNdkSMrwubOGUUINEDMajzc9edARQ27V/8WsSTDLHUk/DobqKsviwyVKUWRmgiyXrrBXVCReUqFyn7K5GpT6A0cxPV9Skc8BaDPbMlUJSL7pIaN+rsHRDlmx22PuMCq6xzTkLkHqBQuu/aCbCJtAB31jNlwrpSImkBSZl+SM/8DSt1sUgUiC9Fo1pdKVUr5TvKC0/Eie44MoaZMUYVlvv5dmq922ZQAMMfvUdK5CunEegkD8PnXiKX7S+HSrWrZ6ipj7kMZmEQikjJI3ZedOGjodXsfx2wHPSiAiR8ugxeE7rVrePKxrMb8iLcIZV1m08oeWLsc8rHEY4wDidWPNxJdFzTMu2LfwnTqsj5VeYpbY7W6uawpQAzdYc X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AS4PR08MB7901.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(366004)(376002)(136003)(346002)(451199015)(33656002)(84970400001)(86362001)(2906002)(38100700002)(122000001)(7696005)(186003)(38070700005)(478600001)(6506007)(91956017)(9686003)(26005)(6636002)(316002)(71200400001)(4326008)(76116006)(8676002)(66946007)(64756008)(66446008)(66476007)(66556008)(6862004)(52536014)(5660300002)(41300700001)(8936002)(55016003)(14773001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Oct 2022 12:23:26.4022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b5ae43c9-3a58-4554-875d-08dab295e3a4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR03FT021.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6524 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Richard,=0A= =0A= > Can you do the aarch64_mov_imm changes as a separate patch?=A0 It's diffi= cult=0A= > to review the two changes folded together like this.=0A= =0A= Sure, I'll send a separate patch. So here is version 2 again:=0A= =0A= [PATCH v2][AArch64] Improve immediate expansion [PR106583]=0A= =0A= Improve immediate expansion of immediates which can be created from a=0A= bitmask immediate and 2 MOVKs. Simplify, refactor and improve=0A= efficiency of bitmask checks. This reduces the number of 4-instruction=0A= immediates in SPECINT/FP by 10-15%.=0A= =0A= Passes regress, OK for commit?=0A= =0A= gcc/ChangeLog:=0A= =0A= PR target/106583=0A= * config/aarch64/aarch64.cc (aarch64_internal_mov_immediate)=0A= Add support for a bitmask immediate with 2 MOVKs.=0A= (aarch64_check_bitmask): New function after refactorization.=0A= (aarch64_replicate_bitmask_imm): Remove function, merge into...=0A= (aarch64_bitmask_imm): Simplify replication of small modes.=0A= Split function into 64-bit only version for efficiency.=0A= =0A= gcc/testsuite:=0A= PR target/106583=0A= * gcc.target/aarch64/pr106583.c: Add new test.=0A= =0A= ---=0A= =0A= diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc= =0A= index 926e81f028c82aac9a5fecc18f921f84399c24ae..b2d9c7380975028131d0fe731a9= 7b3909874b87b 100644=0A= --- a/gcc/config/aarch64/aarch64.cc=0A= +++ b/gcc/config/aarch64/aarch64.cc=0A= @@ -306,6 +306,7 @@ static machine_mode aarch64_simd_container_mode (scalar= _mode, poly_int64);=0A= static bool aarch64_print_address_internal (FILE*, machine_mode, rtx,=0A= aarch64_addr_query_type);=0A= static HOST_WIDE_INT aarch64_clamp_to_uimm12_shift (HOST_WIDE_INT val);=0A= +static bool aarch64_bitmask_imm (unsigned HOST_WIDE_INT);=0A= =0A= /* The processor for which instructions should be scheduled. */=0A= enum aarch64_processor aarch64_tune =3D cortexa53;=0A= @@ -5502,6 +5503,30 @@ aarch64_output_sve_vector_inc_dec (const char *opera= nds, rtx x)=0A= factor, nelts_per_vq);=0A= }=0A= =0A= +/* Return true if the immediate VAL can be a bitfield immediate=0A= + by changing the given MASK bits in VAL to zeroes, ones or bits=0A= + from the other half of VAL. Return the new immediate in VAL2. */=0A= +static inline bool=0A= +aarch64_check_bitmask (unsigned HOST_WIDE_INT val,=0A= + unsigned HOST_WIDE_INT &val2,=0A= + unsigned HOST_WIDE_INT mask)=0A= +{=0A= + val2 =3D val & ~mask;=0A= + if (val2 !=3D val && aarch64_bitmask_imm (val2))=0A= + return true;=0A= + val2 =3D val | mask;=0A= + if (val2 !=3D val && aarch64_bitmask_imm (val2))=0A= + return true;=0A= + val =3D val & ~mask;=0A= + val2 =3D val | (((val >> 32) | (val << 32)) & mask);=0A= + if (val2 !=3D val && aarch64_bitmask_imm (val2))=0A= + return true;=0A= + val2 =3D val | (((val >> 16) | (val << 48)) & mask);=0A= + if (val2 !=3D val && aarch64_bitmask_imm (val2))=0A= + return true;=0A= + return false;=0A= +}=0A= +=0A= static int=0A= aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,=0A= scalar_int_mode mode)=0A= @@ -5568,36 +5593,43 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, = bool generate,=0A= one_match =3D ((~val & mask) =3D=3D 0) + ((~val & (mask << 16)) =3D=3D 0= ) +=0A= ((~val & (mask << 32)) =3D=3D 0) + ((~val & (mask << 48)) =3D=3D 0);= =0A= =0A= - if (zero_match !=3D 2 && one_match !=3D 2)=0A= + if (zero_match < 2 && one_match < 2)=0A= {=0A= /* Try emitting a bitmask immediate with a movk replacing 16 bits.= =0A= For a 64-bit bitmask try whether changing 16 bits to all ones or= =0A= zeroes creates a valid bitmask. To check any repeated bitmask,= =0A= try using 16 bits from the other 32-bit half of val. */=0A= =0A= - for (i =3D 0; i < 64; i +=3D 16, mask <<=3D 16)=0A= - {=0A= - val2 =3D val & ~mask;=0A= - if (val2 !=3D val && aarch64_bitmask_imm (val2, mode))=0A= - break;=0A= - val2 =3D val | mask;=0A= - if (val2 !=3D val && aarch64_bitmask_imm (val2, mode))=0A= - break;=0A= - val2 =3D val2 & ~mask;=0A= - val2 =3D val2 | (((val2 >> 32) | (val2 << 32)) & mask);=0A= - if (val2 !=3D val && aarch64_bitmask_imm (val2, mode))=0A= - break;=0A= - }=0A= - if (i !=3D 64)=0A= - {=0A= - if (generate)=0A= + for (i =3D 0; i < 64; i +=3D 16)=0A= + if (aarch64_check_bitmask (val, val2, mask << i))=0A= + {=0A= + if (generate)=0A= + {=0A= + emit_insn (gen_rtx_SET (dest, GEN_INT (val2)));=0A= + emit_insn (gen_insv_immdi (dest, GEN_INT (i),=0A= + GEN_INT ((val >> i) & 0xffff)));= =0A= + }=0A= + return 2;=0A= + }=0A= + }=0A= +=0A= + /* Try a bitmask plus 2 movk to generate the immediate in 3 instructions= . */=0A= + if (zero_match + one_match =3D=3D 0)=0A= + {=0A= + for (i =3D 0; i < 48; i +=3D 16)=0A= + for (int j =3D i + 16; j < 64; j +=3D 16)=0A= + if (aarch64_check_bitmask (val, val2, (mask << i) | (mask << j)))= =0A= {=0A= - emit_insn (gen_rtx_SET (dest, GEN_INT (val2)));=0A= - emit_insn (gen_insv_immdi (dest, GEN_INT (i),=0A= - GEN_INT ((val >> i) & 0xffff)));= =0A= + if (generate)=0A= + {=0A= + emit_insn (gen_rtx_SET (dest, GEN_INT (val2)));=0A= + emit_insn (gen_insv_immdi (dest, GEN_INT (i),=0A= + GEN_INT ((val >> i) & 0xffff))= );=0A= + emit_insn (gen_insv_immdi (dest, GEN_INT (j),=0A= + GEN_INT ((val >> j) & 0xffff= )));=0A= + }=0A= + return 3;=0A= }=0A= - return 2;=0A= - }=0A= }=0A= =0A= /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones whi= ch=0A= @@ -10168,22 +10200,6 @@ aarch64_movk_shift (const wide_int_ref &and_val,= =0A= return -1;=0A= }=0A= =0A= -/* VAL is a value with the inner mode of MODE. Replicate it to fill a=0A= - 64-bit (DImode) integer. */=0A= -=0A= -static unsigned HOST_WIDE_INT=0A= -aarch64_replicate_bitmask_imm (unsigned HOST_WIDE_INT val, machine_mode mo= de)=0A= -{=0A= - unsigned int size =3D GET_MODE_UNIT_PRECISION (mode);=0A= - while (size < 64)=0A= - {=0A= - val &=3D (HOST_WIDE_INT_1U << size) - 1;=0A= - val |=3D val << size;=0A= - size *=3D 2;=0A= - }=0A= - return val;=0A= -}=0A= -=0A= /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */=0A= =0A= static const unsigned HOST_WIDE_INT bitmask_imm_mul[] =3D=0A= @@ -10196,26 +10212,42 @@ static const unsigned HOST_WIDE_INT bitmask_imm_m= ul[] =3D=0A= };=0A= =0A= =0A= -/* Return true if val is a valid bitmask immediate. */=0A= -=0A= +/* Return true if val is a valid bitmask immediate for any mode. */=0A= bool=0A= aarch64_bitmask_imm (HOST_WIDE_INT val_in, machine_mode mode)=0A= {=0A= - unsigned HOST_WIDE_INT val, tmp, mask, first_one, next_one;=0A= + if (mode =3D=3D DImode)=0A= + return aarch64_bitmask_imm (val_in);=0A= +=0A= + unsigned HOST_WIDE_INT val =3D val_in;=0A= +=0A= + if (mode =3D=3D SImode)=0A= + return aarch64_bitmask_imm ((val & 0xffffffff) | (val << 32));=0A= +=0A= + /* Replicate small immediates to fit 64 bits. */=0A= + int size =3D GET_MODE_UNIT_PRECISION (mode);=0A= + val &=3D (HOST_WIDE_INT_1U << size) - 1;=0A= + val *=3D bitmask_imm_mul[__builtin_clz (size) - 26];=0A= +=0A= + return aarch64_bitmask_imm (val);=0A= +}=0A= +=0A= +=0A= +/* Return true if 64-bit val is a valid bitmask immediate. */=0A= +=0A= +static bool=0A= +aarch64_bitmask_imm (unsigned HOST_WIDE_INT val)=0A= +{=0A= + unsigned HOST_WIDE_INT tmp, mask, first_one, next_one;=0A= int bits;=0A= =0A= /* Check for a single sequence of one bits and return quickly if so.=0A= The special cases of all ones and all zeroes returns false. */=0A= - val =3D aarch64_replicate_bitmask_imm (val_in, mode);=0A= tmp =3D val + (val & -val);=0A= =0A= if (tmp =3D=3D (tmp & -tmp))=0A= return (val + 1) > 1;=0A= =0A= - /* Replicate 32-bit immediates so we can treat them as 64-bit. */=0A= - if (mode =3D=3D SImode)=0A= - val =3D (val << 32) | (val & 0xffffffff);=0A= -=0A= /* Invert if the immediate doesn't start with a zero bit - this means we= =0A= only need to search for sequences of one bits. */=0A= if (val & 1)=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/pr106583.c b/gcc/testsuite/gc= c.target/aarch64/pr106583.c=0A= new file mode 100644=0A= index 0000000000000000000000000000000000000000..0f931580817d78dc1cc58f03b25= 1bd21bec71f59=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/aarch64/pr106583.c=0A= @@ -0,0 +1,41 @@=0A= +/* { dg-do assemble } */=0A= +/* { dg-options "-O2 --save-temps" } */=0A= +=0A= +long f1 (void)=0A= +{=0A= + return 0x7efefefefefefeff;=0A= +}=0A= +=0A= +long f2 (void)=0A= +{=0A= + return 0x12345678aaaaaaaa;=0A= +}=0A= +=0A= +long f3 (void)=0A= +{=0A= + return 0x1234cccccccc5678;=0A= +}=0A= +=0A= +long f4 (void)=0A= +{=0A= + return 0x7777123456787777;=0A= +}=0A= +=0A= +long f5 (void)=0A= +{=0A= + return 0x5555555512345678;=0A= +}=0A= +=0A= +long f6 (void)=0A= +{=0A= + return 0x1234bbbb5678bbbb;=0A= +}=0A= +=0A= +long f7 (void)=0A= +{=0A= + return 0x4444123444445678;=0A= +}=0A= +=0A= +=0A= +/* { dg-final { scan-assembler-times {\tmovk\t} 14 } } */=0A= +/* { dg-final { scan-assembler-times {\tmov\t} 7 } } */=0A=