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Wed, 12 Oct 2022 14:38:44 +0000 From: Wilco Dijkstra To: Richard Sandiford CC: GCC Patches , Kyrylo Tkachov Subject: Re: [PATCH][AArch64] Improve bit tests [PR105773] Thread-Topic: [PATCH][AArch64] Improve bit tests [PR105773] Thread-Index: AQHY2LXhPGQzp4WWbkOKTP58dpaxFa4ABQOLgArXJQo= Date: Wed, 12 Oct 2022 14:38:44 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: AS4PR08MB7901:EE_|DBAPR08MB5559:EE_|VE1EUR03FT007:EE_|AS8PR08MB8657:EE_ X-MS-Office365-Filtering-Correlation-Id: bc3efdc9-61be-4a70-adf0-08daac5f7f14 x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Bn5XQvBc8Z1C7Pqah+RMyvPFP3r2vNFGUWERa3JiHfOX0H1RyIMui3gk61nAXPlmKMZMYDv3xovBLM1W0HjgPXmd0/w5mLIhlj87+PS1pS+n0xvTcsDRWnGwsSxKQ9RwY3e+yu1FAfK1OrMnJVnXj8Dv0nIyGmrvdkpgWs3xDXVvlMo8YDepvXGTrWPmNcT31K1Iy9OCNRSH/awD74bV8dBPRIREAHlkr0YpK42A2UO+V4xP5Vw7nVCzCkXgzB96My3vKr6ovAokhM7co0Q+Hlaa+OO1RQbciE5GlGiRPhKgRHxbJaF8wO4JEO/+jXhCKEfylvW9p53xnm6gHfFWDN2b2ufPdyRpWPvNIAzhn4MGEvKn87zABYvikL70NcvgyYZRaktIaoTe6fG9iptaYbO6v7ATvomIU450OF69FhdIf8v+4tsgCbgYGi9NlKsj8EcCz2GiA5zgI5w91nNsVeYxi1kcvEUm9TeBwQzJWHk6qks2h4cGhvnJMWDp7mgDJqDzdYdo2tQ+VbjZEeonz6oG6RkrPTczyJLY/a6LpGa1fwWV1bM55QH9yGlR9lKqBvi8ySzZQkblYykYHtplJCEos2ZcSDrXAooRvP+irdRo+D3KKhN/ZzkZakxmqIegvPNkWoHg7jUgV7LtJYIQGxHyQh+VvcXxcEoGodJJHRaJQep1ldGyOQzJV5uhQdzxpTqM+Swe5PmlPlQtXhdgCfAztNkJkMI/RjttIgRSH18MqtnVpA8+6LKMLVIj3p+oW3xjoXjfYIZ+tgpWj2NFVOwADtC2Bpqr4eWBJZKIKc81pj04xAI9uASwQbT0rvLz5pYmhVXiaqzEKyr3U9BiQg== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AS4PR08MB7901.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(39850400004)(346002)(366004)(136003)(396003)(376002)(451199015)(38100700002)(122000001)(86362001)(91956017)(7696005)(9686003)(6506007)(64756008)(66446008)(66476007)(66556008)(66946007)(76116006)(8676002)(478600001)(26005)(71200400001)(4326008)(6636002)(316002)(54906003)(2906002)(41300700001)(6862004)(186003)(5660300002)(52536014)(30864003)(8936002)(38070700005)(33656002)(55016003)(84970400001)(579004);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2022 14:38:57.8872 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc3efdc9-61be-4a70-adf0-08daac5f7f14 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT007.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8657 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Richard,=0A= =0A= > Realise this is awkward, but: CC_NZmode is for operations that set only= =0A= > the N and Z flags to useful values.=A0 If we want to take advantage of V= =0A= > being zero then I think we need a different mode.=0A= >=0A= > We can't go all the way to CCmode because the carry flag has the opposite= =0A= > value compared to subtraction.=A0 But we could have either:=0A= > =0A= > * CC_INVC (inverted carry) that handles all comparisons, including the=0A= > =A0 redundant unsigned comparisons=0A= >=0A= > * CC_NZV=0A= >=0A= > Guess I've got a slight preference for CC_INVC, but either would be OK IM= O.=0A= =0A= I've added CC_NZV since that's easier to understand and unsigned comparison= s=0A= with zero are always changed into equality comparisons. There were a few ca= ses=0A= where CC_NZ mode was used rather than CC_Z, so I changed those too.=0A= =0A= Cheers,=0A= Wilco=0A= =0A= v2: Add new CC_NZV mode for cmp+and.=0A= =0A= Since AArch64 sets all flags on logical operations, comparisons with zero= =0A= can be combined into an AND even if the condition is LE or GT. Add a new=0A= CC_NZV mode used by ANDS/BICS/TST instructions.=0A= =0A= Passes regress, OK for commit?=0A= =0A= gcc/ChangeLog:=0A= =0A= PR target/105773=0A= * config/aarch64/aarch64.cc (aarch64_select_cc_mode): Allow=0A= GT/LE for merging compare with zero into AND.=0A= (aarch64_get_condition_code_1): Add CC_NZVmode support.=0A= * config/aarch64/aarch64-modes.def: Add CC_NZV.=0A= * config/aarch64/aarch64.md: Use CC_NZV in cmp+and patterns.=0A= =0A= gcc/testsuite:=0A= PR target/105773=0A= * gcc.target/aarch64/ands_2.c: Test for ANDS.=0A= * gcc.target/aarch64/bics_2.c: Test for BICS.=0A= * gcc.target/aarch64/tst_2.c: Test for TST.=0A= * gcc.target/aarch64/tst_imm_split_1.c: Fix test.=0A= =0A= ---=0A= =0A= diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarc= h64-modes.def=0A= index d3c9b74434cd2c0d0cb1a2fd26af8c0bf38a4cfa..0fd4c32ad0bd09f8651d1b8a773= 78fa4504ff488 100644=0A= --- a/gcc/config/aarch64/aarch64-modes.def=0A= +++ b/gcc/config/aarch64/aarch64-modes.def=0A= @@ -35,6 +35,7 @@ CC_MODE (CCFPE);=0A= CC_MODE (CC_SWP);=0A= CC_MODE (CC_NZC); /* Only N, Z and C bits of condition flags are valid.= =0A= (Used with SVE predicate tests.) */=0A= +CC_MODE (CC_NZV); /* Only N, Z and V bits of condition flags are valid. = */=0A= CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */= =0A= CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */=0A= CC_MODE (CC_C); /* C represents unsigned overflow of a simple addition= . */=0A= diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc= =0A= index 3a4b1f6987487e959648a343bb25180ea419f397..600e0f41d51242a6f100b3643ce= 8421ea116ec5c 100644=0A= --- a/gcc/config/aarch64/aarch64.cc=0A= +++ b/gcc/config/aarch64/aarch64.cc=0A= @@ -11284,7 +11284,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y= )=0A= if (y =3D=3D const0_rtx && (REG_P (x) || SUBREG_P (x))=0A= && (code =3D=3D EQ || code =3D=3D NE)=0A= && (mode_x =3D=3D HImode || mode_x =3D=3D QImode))=0A= - return CC_NZmode;=0A= + return CC_Zmode;=0A= =0A= /* Similarly, comparisons of zero_extends from shorter modes can=0A= be performed using an ANDS with an immediate mask. */=0A= @@ -11292,15 +11292,22 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx= y)=0A= && (mode_x =3D=3D SImode || mode_x =3D=3D DImode)=0A= && (GET_MODE (XEXP (x, 0)) =3D=3D HImode || GET_MODE (XEXP (x, 0)) = =3D=3D QImode)=0A= && (code =3D=3D EQ || code =3D=3D NE))=0A= - return CC_NZmode;=0A= + return CC_Zmode;=0A= +=0A= + /* ANDS/BICS/TST support equality and all signed comparisons. */=0A= + if ((mode_x =3D=3D SImode || mode_x =3D=3D DImode)=0A= + && y =3D=3D const0_rtx=0A= + && (code_x =3D=3D AND || (code_x =3D=3D ZERO_EXTRACT && CONST_INT_P = (XEXP (x, 1))=0A= + && CONST_INT_P (XEXP (x, 2))))=0A= + && (code =3D=3D EQ || code =3D=3D NE || code =3D=3D LT || code =3D= =3D GE=0A= + || code =3D=3D GT || code =3D=3D LE))=0A= + return CC_NZVmode;=0A= =0A= + /* ADDS/SUBS correctly set N and Z flags. */=0A= if ((mode_x =3D=3D SImode || mode_x =3D=3D DImode)=0A= && y =3D=3D const0_rtx=0A= && (code =3D=3D EQ || code =3D=3D NE || code =3D=3D LT || code =3D= =3D GE)=0A= - && (code_x =3D=3D PLUS || code_x =3D=3D MINUS || code_x =3D=3D AND= =0A= - || code_x =3D=3D NEG=0A= - || (code_x =3D=3D ZERO_EXTRACT && CONST_INT_P (XEXP (x, 1))=0A= - && CONST_INT_P (XEXP (x, 2)))))=0A= + && (code_x =3D=3D PLUS || code_x =3D=3D MINUS || code_x =3D=3D NEG))= =0A= return CC_NZmode;=0A= =0A= /* A compare with a shifted operand. Because of canonicalization,=0A= @@ -11437,6 +11444,19 @@ aarch64_get_condition_code_1 (machine_mode mode, e= num rtx_code comp_code)=0A= }=0A= break;=0A= =0A= + case E_CC_NZVmode:=0A= + switch (comp_code)=0A= + {=0A= + case NE: return AARCH64_NE;=0A= + case EQ: return AARCH64_EQ;=0A= + case GE: return AARCH64_PL;=0A= + case LT: return AARCH64_MI;=0A= + case GT: return AARCH64_GT;=0A= + case LE: return AARCH64_LE;=0A= + default: return -1;=0A= + }=0A= + break;=0A= +=0A= case E_CC_NZmode:=0A= switch (comp_code)=0A= {=0A= diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md= =0A= index 23ceca48543d23b85beea1f0bf98ef83051d80b6..cc58373144890c617ff6ce16ca3= 7d14e0617bf3b 100644=0A= --- a/gcc/config/aarch64/aarch64.md=0A= +++ b/gcc/config/aarch64/aarch64.md=0A= @@ -4513,8 +4513,8 @@ (define_insn "*si3_uxtw"=0A= )=0A= =0A= (define_insn "*and3_compare0"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (match_operand:GPI 1 "register_operand" "%r,r")=0A= (match_operand:GPI 2 "aarch64_logical_operand" "r,"))=0A= (const_int 0)))=0A= @@ -4529,8 +4529,8 @@ (define_insn "*and3_compare0"=0A= =0A= ;; zero_extend version of above=0A= (define_insn "*andsi3_compare0_uxtw"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:SI (match_operand:SI 1 "register_operand" "%r,r")=0A= (match_operand:SI 2 "aarch64_logical_operand" "r,K"))=0A= (const_int 0)))=0A= @@ -4544,8 +4544,8 @@ (define_insn "*andsi3_compare0_uxtw"=0A= )=0A= =0A= (define_insn "*and_3_compare0"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (SHIFT:GPI=0A= (match_operand:GPI 1 "register_operand" "r")=0A= (match_operand:QI 2 "aarch64_shift_imm_" "n"))=0A= @@ -4564,8 +4564,8 @@ (define_insn "*and_3_compare0"=0A= =0A= ;; zero_extend version of above=0A= (define_insn "*and_si3_compare0_uxtw"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:SI (SHIFT:SI=0A= (match_operand:SI 1 "register_operand" "r")=0A= (match_operand:QI 2 "aarch64_shift_imm_si" "n"))=0A= @@ -4769,8 +4769,8 @@ (define_insn_and_split "*xor_one_cmpl3"=0A= )=0A= =0A= (define_insn "*and_one_cmpl3_compare0"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (not:GPI=0A= (match_operand:GPI 1 "register_operand" "r"))=0A= (match_operand:GPI 2 "register_operand" "r"))=0A= @@ -4784,8 +4784,8 @@ (define_insn "*and_one_cmpl3_compare0"=0A= =0A= ;; zero_extend version of above=0A= (define_insn "*and_one_cmplsi3_compare0_uxtw"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:SI (not:SI=0A= (match_operand:SI 1 "register_operand" "r"))=0A= (match_operand:SI 2 "register_operand" "r"))=0A= @@ -4798,8 +4798,8 @@ (define_insn "*and_one_cmplsi3_compare0_uxtw"=0A= )=0A= =0A= (define_insn "*and_one_cmpl3_compare0_no_reuse"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (not:GPI=0A= (match_operand:GPI 0 "register_operand" "r"))=0A= (match_operand:GPI 1 "register_operand" "r"))=0A= @@ -4877,8 +4877,8 @@ (define_insn "*eor_one_cmpl_sidi3_alt_ze= "=0A= )=0A= =0A= (define_insn "*and_one_cmpl_3_compare0"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (not:GPI=0A= (SHIFT:GPI=0A= (match_operand:GPI 1 "register_operand" "r")=0A= @@ -4900,8 +4900,8 @@ (define_insn "*and_one_cmpl_3_comp= are0"=0A= =0A= ;; zero_extend version of above=0A= (define_insn "*and_one_cmpl_si3_compare0_uxtw"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:SI (not:SI=0A= (SHIFT:SI=0A= (match_operand:SI 1 "register_operand" "r")=0A= @@ -4922,8 +4922,8 @@ (define_insn "*and_one_cmpl_si3_compare0= _uxtw"=0A= )=0A= =0A= (define_insn "*and_one_cmpl_3_compare0_no_reuse"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (not:GPI=0A= (SHIFT:GPI=0A= (match_operand:GPI 0 "register_operand" "r")=0A= @@ -5028,8 +5028,8 @@ (define_insn_and_split "ctz2"=0A= ")=0A= =0A= (define_insn "*and_compare0"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_Z CC_REGNUM)=0A= + (compare:CC_Z=0A= (match_operand:SHORT 0 "register_operand" "r")=0A= (const_int 0)))]=0A= ""=0A= @@ -5038,8 +5038,8 @@ (define_insn "*and_compare0"=0A= )=0A= =0A= (define_insn "*ands_compare0"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_Z CC_REGNUM)=0A= + (compare:CC_Z=0A= (zero_extend:GPI (match_operand:SHORT 1 "register_operand" "r"))=0A= (const_int 0)))=0A= (set (match_operand:GPI 0 "register_operand" "=3Dr")=0A= @@ -5050,8 +5050,8 @@ (define_insn "*ands_compare0"=0A= )=0A= =0A= (define_insn "*and3nr_compare0"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (match_operand:GPI 0 "register_operand" "%r,r")=0A= (match_operand:GPI 1 "aarch64_logical_operand" "r,"))=0A= (const_int 0)))]=0A= @@ -5063,24 +5063,24 @@ (define_insn "*and3nr_compare0"=0A= )=0A= =0A= (define_split=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (match_operand:GPI 0 "register_operand")=0A= (match_operand:GPI 1 "aarch64_mov_imm_operand"))=0A= (const_int 0)))=0A= (clobber (match_operand:SI 2 "register_operand"))]=0A= ""=0A= [(set (match_dup 2) (match_dup 1))=0A= - (set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + (set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (match_dup 0)=0A= (match_dup 2))=0A= (const_int 0)))]=0A= )=0A= =0A= (define_insn "*and3nr_compare0_zextract"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (zero_extract:GPI (match_operand:GPI 0 "register_operand" "r")=0A= (match_operand:GPI 1 "const_int_operand" "n")=0A= (match_operand:GPI 2 "const_int_operand" "n"))=0A= @@ -5101,8 +5101,8 @@ (define_insn "*and3nr_compare0_zextract"=0A= )=0A= =0A= (define_insn "*and_3nr_compare0"=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (SHIFT:GPI=0A= (match_operand:GPI 0 "register_operand" "r")=0A= (match_operand:QI 1 "aarch64_shift_imm_" "n"))=0A= @@ -5118,8 +5118,8 @@ (define_insn "*and_3nr_compare0"= =0A= )=0A= =0A= (define_split=0A= - [(set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + [(set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (SHIFT:GPI=0A= (match_operand:GPI 0 "register_operand")=0A= (match_operand:QI 1 "aarch64_shift_imm_"))=0A= @@ -5128,8 +5128,8 @@ (define_split=0A= (clobber (match_operand:SI 3 "register_operand"))]=0A= ""=0A= [(set (match_dup 3) (match_dup 2))=0A= - (set (reg:CC_NZ CC_REGNUM)=0A= - (compare:CC_NZ=0A= + (set (reg:CC_NZV CC_REGNUM)=0A= + (compare:CC_NZV=0A= (and:GPI (SHIFT:GPI=0A= (match_dup 0)=0A= (match_dup 1))=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/ands_2.c b/gcc/testsuite/gcc.= target/aarch64/ands_2.c=0A= index b061b1dfc59c1847cb799a1e49f8e5fc53bf2f14..c8763f234c5f7d19ef9c222756a= b5e8a6eaae6fe 100644=0A= --- a/gcc/testsuite/gcc.target/aarch64/ands_2.c=0A= +++ b/gcc/testsuite/gcc.target/aarch64/ands_2.c=0A= @@ -8,8 +8,7 @@ ands_si_test1 (int a, int b, int c)=0A= {=0A= int d =3D a & b;=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]= +" } } */=0A= - /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" }= } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -21,12 +20,11 @@ ands_si_test2 (int a, int b, int c)=0A= {=0A= int d =3D a & 0x99999999;=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986= 919" } } */=0A= - /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" = } } */=0A= - if (d <=3D 0)=0A= - return a + c;=0A= - else=0A= + /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919"= } } */=0A= + if (d > 0)=0A= return b + d + c;=0A= + else=0A= + return a + c;=0A= }=0A= =0A= int=0A= @@ -34,8 +32,7 @@ ands_si_test3 (int a, int b, int c)=0A= {=0A= int d =3D a & (b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]= +, lsl 3" } } */=0A= - /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, ls= l 3" } } */=0A= + /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, l= sl 3" } } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -49,8 +46,7 @@ ands_di_test1 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & b;=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]= +" } } */=0A= - /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" }= } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -62,12 +58,11 @@ ands_di_test2 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & 0xaaaaaaaaaaaaaaaall;=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, -6148914= 691236517206" } } */=0A= - /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -614891469123= 6517206" } } */=0A= - if (d <=3D 0)=0A= - return a + c;=0A= - else=0A= + /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, -61489146912= 36517206" } } */=0A= + if (d > 0)=0A= return b + d + c;=0A= + else=0A= + return a + c;=0A= }=0A= =0A= s64=0A= @@ -75,8 +70,7 @@ ands_di_test3 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & (b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]= +, lsl 3" } } */=0A= - /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, ls= l 3" } } */=0A= + /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, l= sl 3" } } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/bics_2.c b/gcc/testsuite/gcc.= target/aarch64/bics_2.c=0A= index 9ccae368c1276618bad691c78fb621a9c82794b7..c1f7e87a6121f7b067b7b37b149= da64aa63ebd1a 100644=0A= --- a/gcc/testsuite/gcc.target/aarch64/bics_2.c=0A= +++ b/gcc/testsuite/gcc.target/aarch64/bics_2.c=0A= @@ -8,8 +8,7 @@ bics_si_test1 (int a, int b, int c)=0A= {=0A= int d =3D a & ~b;=0A= =0A= - /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]= +" } } */=0A= - /* { dg-final { scan-assembler-times "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" }= } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -21,12 +20,11 @@ bics_si_test2 (int a, int b, int c)=0A= {=0A= int d =3D a & ~(b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]= +, lsl 3" } } */=0A= - /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, ls= l 3" } } */=0A= - if (d <=3D 0)=0A= - return a + c;=0A= - else=0A= + /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, l= sl 3" } } */=0A= + if (d > 0)=0A= return b + d + c;=0A= + else=0A= + return a + c;=0A= }=0A= =0A= typedef long long s64;=0A= @@ -36,8 +34,7 @@ bics_di_test1 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & ~b;=0A= =0A= - /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]= +" } } */=0A= - /* { dg-final { scan-assembler-times "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" }= } */=0A= if (d <=3D 0)=0A= return a + c;=0A= else=0A= @@ -49,12 +46,11 @@ bics_di_test2 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & ~(b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]= +, lsl 3" } } */=0A= - /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, ls= l 3" } } */=0A= - if (d <=3D 0)=0A= - return a + c;=0A= - else=0A= + /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, l= sl 3" } } */=0A= + if (d > 0)=0A= return b + d + c;=0A= + else=0A= + return a + c;=0A= }=0A= =0A= int=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/tst_2.c b/gcc/testsuite/gcc.t= arget/aarch64/tst_2.c=0A= index c8b28fc5620a9140fee29c4455294af708642d69..3c9bdfd05c4a19e83150f84f454= c3e875c7757d1 100644=0A= --- a/gcc/testsuite/gcc.target/aarch64/tst_2.c=0A= +++ b/gcc/testsuite/gcc.target/aarch64/tst_2.c=0A= @@ -8,8 +8,7 @@ tst_si_test1 (int a, int b, int c)=0A= {=0A= int d =3D a & b;=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+= " } } */=0A= - /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+" } } */=0A= if (d <=3D 0)=0A= return 12;=0A= else=0A= @@ -21,12 +20,11 @@ tst_si_test2 (int a, int b, int c)=0A= {=0A= int d =3D a & 0x99999999;=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, -17179869= 19" } } */=0A= - /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" = } } */=0A= - if (d <=3D 0)=0A= - return 12;=0A= - else=0A= + /* { dg-final { scan-assembler "tst\tw\[0-9\]+, -1717986919" } } */=0A= + if (d > 0)=0A= return 18;=0A= + else=0A= + return 12;=0A= }=0A= =0A= int=0A= @@ -34,8 +32,7 @@ tst_si_test3 (int a, int b, int c)=0A= {=0A= int d =3D a & (b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+= , lsl 3" } } */=0A= - /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, ls= l 3" } } */=0A= + /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */= =0A= if (d <=3D 0)=0A= return 12;=0A= else=0A= @@ -49,8 +46,7 @@ tst_di_test1 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & b;=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+= " } } */=0A= - /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\= ]+" 2 } } */=0A= + /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+" } } */=0A= if (d <=3D 0)=0A= return 12;=0A= else=0A= @@ -62,8 +58,7 @@ tst_di_test2 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & 0xaaaaaaaaaaaaaaaall;=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, -61489146= 91236517206" } } */=0A= - /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -614891469123= 6517206" } } */=0A= + /* { dg-final { scan-assembler "tst\tx\[0-9\]+, -6148914691236517206" } = } */=0A= if (d <=3D 0)=0A= return 12;=0A= else=0A= @@ -75,12 +70,11 @@ tst_di_test3 (s64 a, s64 b, s64 c)=0A= {=0A= s64 d =3D a & (b << 3);=0A= =0A= - /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+= , lsl 3" } } */=0A= - /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, ls= l 3" } } */=0A= - if (d <=3D 0)=0A= - return 12;=0A= - else=0A= + /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */= =0A= + if (d > 0)=0A= return 18;=0A= + else=0A= + return 12;=0A= }=0A= =0A= int=0A= diff --git a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c b/gcc/tests= uite/gcc.target/aarch64/tst_imm_split_1.c=0A= index 33a2c0f45afadb8fc9488f847f296ec0e690c049..e456e823593fbe507a8a67b5115= a45712e40f80e 100644=0A= --- a/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c=0A= +++ b/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c=0A= @@ -14,5 +14,4 @@ g (unsigned char *p)=0A= }=0A= =0A= /* { dg-final { scan-assembler-not "and\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+.*= " } } */=0A= -/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+" } } = */=0A= -/* { dg-final { scan-assembler "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+, lsr = 4" } } */=0A= +/* { dg-final { scan-assembler-times "tst\\t\[xw\]\[0-9\]+, \[xw\]\[0-9\]+= " 2 } } */=0A= =0A=