From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23201 invoked by alias); 18 Jul 2011 08:46:32 -0000 Received: (qmail 23193 invoked by uid 22791); 18 Jul 2011 08:46:31 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (94.185.240.25) by sourceware.org (qpsmtpd/0.43rc1) with SMTP; Mon, 18 Jul 2011 08:45:59 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 18 Jul 2011 09:45:56 +0100 Received: from [10.1.19.200] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 18 Jul 2011 09:45:55 +0100 Subject: Re: [PATCH] Canonicalize compares in combine [3/3] ARM backend part From: Richard Earnshaw Date: Mon, 18 Jul 2011 09:37:00 -0000 Message-Id: Cc: gcc-patches To: Chung-Lin Tang Mime-Version: 1.0 (iPad Mail 8J3) X-MC-Unique: 111071809455601101 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-07/txt/msg01378.txt.bz2 On 18 Jul 2011, at 07:15, "Chung-Lin Tang" wrote: > On 2011/6/15 09:12 PM, Richard Earnshaw wrote: >> On 22/04/11 16:21, Chung-Lin Tang wrote: >>> Hi Richard, this part's for you. >>>=20 >>> The ARM backend changes needed are very little after the prior patches, >>> basically just a case in arm_canonicalize_comparison() to detect >>> (zero_extend:SI (subreg:QI (reg:SI ...) 0)), and swap it into (and:SI >>> (reg:SI) #255). >>>=20 >>> Had we not tried the combine modifications, this testcase probably could >>> have also be solved by implementing another version of the corresponding >>> *andsi3_compare0/_scratch patterns, with ZERO_EXTEND in the body, and >>> "ands" in the output assembly. Maybe that's an acceptable solution too.= .. >>>=20 >>> About the (ab)use of CANONICALIZE_COMPARISON, if it really should be >>> another macro/hook, then this ARM patch will need updating, but the code >>> should be similar. >>>=20 >>> Thanks, >>> Chung-Lin >>>=20 >>>=20 >>> 3-arm-parts.diff >>>=20 >>>=20 >>> Index: config/arm/arm.c >>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>> --- config/arm/arm.c (revision 172860) >>> +++ config/arm/arm.c (working copy) >>> @@ -3276,6 +3276,19 @@ >>> return code; >>> } >>>=20 >>> + /* If *op0 is (zero_extend:SI (subreg:QI (reg:SI) 0)) and comparing >>> + with const0_rtx, change it to (and:SI (reg:SI) (const_int 255)), >>> + to facilitate possible combining with a cmp into 'ands'. */ >>> + if (mode =3D=3D SImode >>> + && GET_CODE (*op0) =3D=3D ZERO_EXTEND >>> + && GET_CODE (XEXP (*op0, 0)) =3D=3D SUBREG >>> + && GET_MODE (XEXP (*op0, 0)) =3D=3D QImode >>> + && GET_MODE (SUBREG_REG (XEXP (*op0, 0))) =3D=3D SImode >>> + && SUBREG_BYTE (XEXP (*op0, 0)) =3D=3D 0 >>> + && *op1 =3D=3D const0_rtx) >>> + *op0 =3D gen_rtx_AND (SImode, SUBREG_REG (XEXP (*op0, 0)), >>> + GEN_INT (255)); >>> + >>=20 >> This is wrong for big-endian code. You should use subreg_lowpart_p to >> check the subreg expression (after you've checked that you do have a >> subreg, of course). >>=20 >> R. >>=20 >=20 > Hi Richard, thanks for catching that. I've updated the patch, and > cross-tested again under both arm/armeb-Linux. >=20 > I changed the testcase to use -march=3Darmv6t2 instead of armv6, as the > latter makes the testcase FAIL when configured as --with-mode=3Dthumb. >=20 > Is this now okay? >=20 The patch to arm.c is ok, but the change to the test is not as it will caus= e problems with multilib testing. A better fix is to skip the test if the = target is thumb1. The other test needs a similar check as it seems to expect a movs instructi= on. R. > Thanks, > Chung-Lin >