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From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: kito.cheng <kito.cheng@gmail.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>,
	 palmer <palmer@dabbelt.com>,
	 richard.sandiford <richard.sandiford@arm.com>,
	 rguenther <rguenther@suse.de>,
	 jeffreyalaw <jeffreyalaw@gmail.com>
Subject: Re: Re: [PATCH 2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern
Date: Fri, 7 Apr 2023 09:40:23 +0800	[thread overview]
Message-ID: <B5D05D0E0EB0F9B3+2023040709402331558796@rivai.ai> (raw)
In-Reply-To: <CA+yXCZCyPD4wXuBfQA=82q-qoeAcK91SSG31fc0uhq2cH7L2=Q@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 11001 bytes --]

Address all comments, and fix all of them in these splitted patches:

These 5 patches only including RISC-V port changes:
https://patchwork.sourceware.org/project/gcc/patch/20230407011143.46004-1-juzhe.zhong@rivai.ai/ 
https://patchwork.sourceware.org/project/gcc/patch/20230407012129.63142-1-juzhe.zhong@rivai.ai/ 
https://patchwork.sourceware.org/project/gcc/patch/20230407012503.65215-1-juzhe.zhong@rivai.ai/ 
https://patchwork.sourceware.org/project/gcc/patch/20230407013413.127686-1-juzhe.zhong@rivai.ai/ 
https://patchwork.sourceware.org/project/gcc/patch/20230407013701.129875-1-juzhe.zhong@rivai.ai/ 

I would like to resend a patch for pure middle-end changes for WHILE_LEN pattern support in Middle-end.
Ignore this serise of patches.

Thanks!


juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-04-07 00:04
To: juzhe.zhong
CC: gcc-patches; palmer; richard.sandiford; rguenther; jeffreyalaw
Subject: Re: [PATCH 2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern
Is changes for riscv-vsetvl.cc necessary for autovec? or is it
additional optimization for the autovec use case? I would suggest
splitting that if it's later one.
 
And plz split out fixed-vlmax part into separated patch, that would be
easier to review.
 
On Thu, Apr 6, 2023 at 10:44 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add compile option for RVV auto-vectorization.
>         (enum riscv_autovec_lmul_enum): Ditto.
>         * config/riscv/riscv-protos.h (get_vector_mode): Remove unused global function.
>         (preferred_simd_mode): Enable basic auto-vectorization for RVV.
>         (expand_while_len): Enable while_len pattern.
>         * config/riscv/riscv-v.cc (get_avl_type_rtx): Ditto.
>         (autovec_use_vlmax_p): New function.
>         (preferred_simd_mode): New function.
>         (expand_while_len): Ditto.
>         * config/riscv/riscv-vector-switch.def (ENTRY): Disable SEW = 64 for MIN_VLEN > 32 but EEW = 32.
 
It's bug fix? plz send a separated patch if it's a bug.
 
>         * config/riscv/riscv-vsetvl.cc (get_all_successors): New function.
>         (get_all_overlap_blocks): Ditto.
>         (local_eliminate_vsetvl_insn): Ditto.
>         (vector_insn_info::skip_avl_compatible_p): Ditto.
>         (vector_insn_info::merge): Ditto.
>         (pass_vsetvl::compute_local_backward_infos): Ehance VSETVL PASS for RVV auto-vectorization.
>         (pass_vsetvl::global_eliminate_vsetvl_p): Ditto.
>         (pass_vsetvl::cleanup_insns): Ditto.
>         * config/riscv/riscv-vsetvl.h: Ditto.
>         * config/riscv/riscv.cc (riscv_convert_vector_bits): Add basic RVV auto-vectorization support.
>         (riscv_preferred_simd_mode): Ditto.
>         (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): Ditto.
>         * config/riscv/riscv.opt: Add compile option.
>         * config/riscv/vector.md: Add RVV auto-vectorization.
>         * config/riscv/autovec.md: New file.
>
> ---
>  gcc/config/riscv/autovec.md              |  63 +++++++
>  gcc/config/riscv/riscv-opts.h            |  16 ++
>  gcc/config/riscv/riscv-protos.h          |   3 +-
>  gcc/config/riscv/riscv-v.cc              |  61 ++++++-
>  gcc/config/riscv/riscv-vector-switch.def |  47 +++--
>  gcc/config/riscv/riscv-vsetvl.cc         | 210 ++++++++++++++++++++++-
>  gcc/config/riscv/riscv-vsetvl.h          |   1 +
>  gcc/config/riscv/riscv.cc                |  34 +++-
>  gcc/config/riscv/riscv.opt               |  40 +++++
>  gcc/config/riscv/vector.md               |   6 +-
>  10 files changed, 457 insertions(+), 24 deletions(-)
>  create mode 100644 gcc/config/riscv/autovec.md
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> new file mode 100644
> index 00000000000..ff616d81586
> --- /dev/null
> +++ b/gcc/config/riscv/autovec.md
> @@ -0,0 +1,63 @@
> +;; Machine description for auto-vectorization using RVV for GNU compiler.
> +;; Copyright (C) 2023-2023 Free Software Foundation, Inc.
 
2023 rather than 2023-2023
 
> +;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
> +
> +;; This file is part of GCC.
> +
> +;; GCC is free software; you can redistribute it and/or modify
> +;; it under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +
> +;; GCC is distributed in the hope that it will be useful,
> +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +;; GNU General Public License for more details.
> +
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3.  If not see
> +;; <http://www.gnu.org/licenses/>.
> +
> +;; =========================================================================
> +;; == While_len
> +;; =========================================================================
> +
> +(define_expand "while_len<mode>"
> +  [(match_operand:P 0 "register_operand")
> +   (match_operand:P 1 "vector_length_operand")
> +   (match_operand:P 2 "")]
> +  "TARGET_VECTOR"
> +{
> +  riscv_vector::expand_while_len (operands);
> +  DONE;
> +})
> +
> +;; =========================================================================
> +;; == Loads/Stores
> +;; =========================================================================
> +
> +;; len_load/len_store is sub-optimal pattern for RVV auto-vectorization support.
 
Google doc say you need a `a`: "is a sub-optimal " :P
 
 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 4611447ddde..7db0deb4dbf 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -184,7 +184,6 @@ enum mask_policy
>  enum tail_policy get_prefer_tail_policy ();
>  enum mask_policy get_prefer_mask_policy ();
>  rtx get_avl_type_rtx (enum avl_type);
> -opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
 
Separated  NFC patch, and Yanzhang's patch has used that, so I think
it's not rush to remove that.
 
 
>  /* Implement TARGET_OPTION_OVERRIDE.  */
> @@ -7076,6 +7084,27 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
>    return shamt == ctz_hwi (mask);
>  }
>
> +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE.  */
> +
> +static machine_mode
> +riscv_preferred_simd_mode (scalar_mode mode)
> +{
> +  /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128
> +     which is -march=rv64gcv. Since GCC loop vectorizer report ICE
> +     when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64x.
> +     in tree-vect-slp.cc:437. Since we have VNx1SImode in -march=*zve32*
 
Reference function name rather than line number, line number might
change, although function name might change too, but that would be
less likely to change than line number.
 
> +     and VNx1DImode in -march=*zve64*, they are enabled in targetm.
> +     vector_mode_supported_p and SLP vectorizer will try to use them.
> +     Currently, we can support auto-vectorization in -march=rv32_zve32x_zvl128b.
> +     Wheras, -march=rv32_zve32x_zvl32b or -march=rv32_zve32x_zvl64b are
> +     disabled.
> +   */
 
What if we use M2 when TARGET_MIN_VLEN=64 and M4 for TARGET_MIN_VLEN = 32?
Or maybe just return word_mode for those cases?
 
> +  if (TARGET_VECTOR && TARGET_MIN_VLEN >= 128)
> +    return riscv_vector::preferred_simd_mode (mode);
> +
> +  return word_mode;
> +}
> +
>  /* Initialize the GCC target structure.  */
>  #undef TARGET_ASM_ALIGNED_HI_OP
>  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> @@ -7327,6 +7356,9 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
>  #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
>  #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
>
> +#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
> +#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode
> +
>  struct gcc_target targetm = TARGET_INITIALIZER;
>
>  #include "gt-riscv.h"
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index ff1dd4ddd4f..7d26e450be5 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -254,3 +254,43 @@ Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213)
>  misa-spec=
>  Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC)
>  Set the version of RISC-V ISA spec.
> +
> +Enum
> +Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum)
> +The RISC-V auto-vectorization preference:
> +
> +EnumValue
> +Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC)
> +
> +EnumValue
> +Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE)
> +
> +EnumValue
> +Enum(riscv_autovec_preference) String(fixed-vlmin) Value(RVV_FIXED_VLMIN)
 
Drop unsupported stuff, and added back once it has implemented.
 
> +
> +EnumValue
> +Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX)
> +
> +-param=riscv-autovec-preference=
> +Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(NO_AUTOVEC)
> +-param=riscv-autovec-preference=<string>       Set the preference of auto-vectorization in RISC-V port.
 
> +-param=riscv-autovec-lmul=
> +Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) Init(RVV_M1)
> +-param=riscv-autovec-lmul=<string>     Set the RVV LMUL of auto-vectorization in RISC-V port.
 
in the RISC-V port
 
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 27bdacc35af..9151a4c9891 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -23,7 +23,7 @@
>  ;; This file include :
>  ;;
>  ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)
> -;; - Auto-vectorization (TBD)
> +;; - Auto-vectorization (autovec.md)
>  ;; - Combine optimization (TBD)
>
>  (include "vector-iterators.md")
> @@ -2015,7 +2015,7 @@
>         riscv_vector::neg_simm5_p (operands[4]),
>         [] (rtx *operands, rtx boardcast_scalar) {
>           emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
> -              operands[2], operands[3], boardcast_scalar, operands[5],
> +              operands[2], boardcast_scalar, operands[3], operands[5],
 
Seems like you mixed some other patch by accidently here.
 
>                operands[6], operands[7], operands[8]));
>          }))
>      DONE;
> @@ -7688,3 +7688,5 @@
>    "vle<sew>ff.v\t%0,%3%p1"
>    [(set_attr "type" "vldff")
>     (set_attr "mode" "<MODE>")])
> +
> +(include "autovec.md")
> --
> 2.36.3
>
 

  reply	other threads:[~2023-04-07  1:40 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-06 14:42 [PATCH 0/3] RISC-V:Enable basic auto-vectorization for RVV juzhe.zhong
2023-04-06 14:42 ` [PATCH 1/3] VECT: Add WHILE_LEN pattern to support decrement IV manipulation for loop vectorizer juzhe.zhong
2023-04-06 14:42 ` [PATCH 2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern juzhe.zhong
2023-04-06 16:04   ` Kito Cheng
2023-04-07  1:40     ` juzhe.zhong [this message]
2023-04-06 14:42 ` [PATCH] RISC-V: Add RVV auto-vectorization testcase juzhe.zhong
2023-04-06 15:36   ` Kito Cheng

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