From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 101332 invoked by alias); 16 Jul 2015 14:20:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 101322 invoked by uid 89); 16 Jul 2015 14:20:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,KAM_ASCII_DIVIDERS,RCVD_IN_DNSWL_LOW,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 16 Jul 2015 14:20:41 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 791B69D033BDF; Thu, 16 Jul 2015 15:20:35 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 16 Jul 2015 15:20:37 +0100 Received: from hhmail02.hh.imgtec.org ([::1]) by hhmail02.hh.imgtec.org ([::1]) with mapi id 14.03.0235.001; Thu, 16 Jul 2015 15:20:37 +0100 From: Robert Suchanek To: "Catherine_Moore@mentor.com" , Matthew Fortune , Prachi Godbole CC: "gcc-patches@gcc.gnu.org" Subject: [PATCH, MIPS] Scheduling for M51xx core family Date: Thu, 16 Jul 2015 14:51:00 -0000 Message-ID: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-IsSubscribed: yes X-SW-Source: 2015-07/txt/msg01412.txt.bz2 Hi, Another patch with a pipeline description but for M51xx cores with two new options introduced: -march=3D{m5100,m5101}. The M5101 is essentially the same as M5100 but mapped to -msoft-float. Ok to apply? Regards, Robert 2015-07-16 Prachi Godbole gcc/ * config/mips/m5100.md: New file. * config/mips/mips-cpus.def (m5100, m5101): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add costs for m5100. * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=3Dm5100 and -march=3Dm5101 to -mips32r5. (MIPS_ARCH_FLOAT_SPEC): Map -m5101 to -msoft-float. (MIPS_ISA_NAN2008_SPEC): Map -march=3Dm51* to -mnan=3D2008 if !-msoft-float. * config/mips/mips.md: Include m5100.md. (processor): Add m5100. * doc/invoke.texi (-march=3D@var{arch}): Add m5100, m5101. --- gcc/config/mips/m5100.md | 220 ++++++++++++++++++++++++++++++++++++= ++++ gcc/config/mips/mips-cpus.def | 2 + gcc/config/mips/mips-tables.opt | 40 ++++---- gcc/config/mips/mips.c | 13 +++ gcc/config/mips/mips.h | 7 +- gcc/config/mips/mips.md | 2 + gcc/doc/invoke.texi | 1 + 7 files changed, 265 insertions(+), 20 deletions(-) create mode 100644 gcc/config/mips/m5100.md diff --git a/gcc/config/mips/m5100.md b/gcc/config/mips/m5100.md new file mode 100644 index 0000000..f860eb2 --- /dev/null +++ b/gcc/config/mips/m5100.md @@ -0,0 +1,220 @@ +;; DFA-based pipeline description for MIPS32 models M5100. +;; +;; Copyright (C) 2015 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_automaton "m51_alu_pipe, m51_mdu_pipe, m51_fpu_pipe") +(define_cpu_unit "m51_mul" "m51_mdu_pipe") +(define_cpu_unit "m51_alu" "m51_alu_pipe") +(define_cpu_unit "m51_fpu" "m51_fpu_pipe") + +;; -------------------------------------------------------------- +;; ALU Instructions +;; -------------------------------------------------------------- + +;; ALU: Logicals +(define_insn_reservation "m51_int_logical" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "logical,move,signext,slt")) + "m51_alu") + +;; Arithmetics +(define_insn_reservation "m51_int" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "arith,const,shift,clz")) + "m51_alu") + +(define_insn_reservation "m51_int_nop" 0 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "nop")) + "nothing") + +;; Conditional move +(define_insn_reservation "m51_int_cmove" 1 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "condmove") + (eq_attr "mode" "SI,DI"))) + "m51_alu") + +;; Call +(define_insn_reservation "m51_int_call" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "call")) + "m51_alu") + +;; branch/jump +(define_insn_reservation "m51_int_jump" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "branch,jump")) + "m51_alu") + +;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs +;; prefetch: prefetch, prefetchx +(define_insn_reservation "m51_int_load" 3 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "load,prefetch,prefetchx")) + "m51_alu") + +;; stores +(define_insn_reservation "m51_int_store" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "store")) + "m51_alu") + +;; -------------------------------------------------------------- +;; MDU Instructions +;; -------------------------------------------------------------- + +;; High performance fully pipelined multiplier +;; MULT to HI/LO +(define_insn_reservation "m51_int_mult" 2 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "imul,imadd")) + "m51_alu+m51_mul*2") + +;; MUL to GPR +(define_insn_reservation "m51_int_mul3" 2 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "imul3")) + "(m51_alu*2)+(m51_mul*2)") + +;; mfhi, mflo +(define_insn_reservation "m51_int_mfhilo" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "mfhi,mflo")) + "m51_mul") + +;; mthi, mtlo +(define_insn_reservation "m51_int_mthilo" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "mthi,mtlo")) + "m51_mul") + +;; div +(define_insn_reservation "m51_int_div_si" 34 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "idiv")) + "m51_alu+m51_mul*34") + +;; -------------------------------------------------------------- +;; Floating Point Instructions +;; -------------------------------------------------------------- + +;; fadd, fabs, fneg +(define_insn_reservation "m51_fadd" 4 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fadd,fabs,fneg")) + "m51_fpu") + +;; fmove +(define_insn_reservation "m51_fmove" 4 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fmove")) + "m51_fpu") + +;; conditional move +(define_insn_reservation "m51_fp_cmove" 4 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "condmove") + (eq_attr "mode" "SF,DF"))) + "m51_fpu") + +;; fload +(define_insn_reservation "m51_fload" 3 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fpload,fpidxload")) + "m51_fpu") + +;; fstore +(define_insn_reservation "m51_fstore" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fpstore,fpidxstore")) + "m51_fpu") + +;; fmul, fmadd +(define_insn_reservation "m51_fmul_sf" 4 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fmul,fmadd") + (eq_attr "mode" "SF"))) + "m51_fpu") + +(define_insn_reservation "m51_fmul_df" 5 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fmul,fmadd") + (eq_attr "mode" "DF"))) + "m51_fpu*2") + +;; fdiv, fsqrt +(define_insn_reservation "m51_fdiv_sf" 17 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fdiv,fsqrt") + (eq_attr "mode" "SF"))) + "m51_fpu*14") + +(define_insn_reservation "m51_fdiv_df" 32 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fdiv,fsqrt") + (eq_attr "mode" "DF"))) + "m51_fpu*29") + +;; frsqrt +(define_insn_reservation "m51_frsqrt_sf" 17 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "frsqrt") + (eq_attr "mode" "SF"))) + "m51_fpu*14") + +(define_insn_reservation "m51_frsqrt_df" 35 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "frsqrt") + (eq_attr "mode" "DF"))) + "m51_fpu*31") + +;; fcmp +(define_insn_reservation "m51_fcmp" 4 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fcmp")) + "m51_fpu") + +;; fcvt +;; cvt.s.d +(define_insn_reservation "m51_fcvt_6" 6 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "D2S"))) + "m51_fpu") + +;; trunc +(define_insn_reservation "m51_fcvt_5" 5 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "D2I,S2I"))) + "m51_fpu") + +;; cvt +(define_insn_reservation "m51_fcvt_4" 4 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "S2D,I2D,I2S"))) + "m51_fpu") + +;; mtc, mfc +(define_insn_reservation "m51_move_to_from_c1" 2 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "mtc, mfc")) + "m51_fpu") diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index fb4bae0..5ed0056 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -149,6 +149,8 @@ MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0) =20 /* MIPS32 Release 5 processors. */ MIPS_CPU ("p5600", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("m5100", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("m5101", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY) =20 /* MIPS64 processors. */ MIPS_CPU ("5kc", PROCESSOR_5KC, 64, 0) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.= opt index 59124a6..bd1d291 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -634,53 +634,59 @@ EnumValue Enum(mips_arch_opt_value) String(p5600) Value(85) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(5kc) Value(86) Canonical +Enum(mips_arch_opt_value) String(m5100) Value(86) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(r5kc) Value(86) +Enum(mips_arch_opt_value) String(m5101) Value(87) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(5kf) Value(87) Canonical +Enum(mips_arch_opt_value) String(5kc) Value(88) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(r5kf) Value(87) +Enum(mips_arch_opt_value) String(r5kc) Value(88) =20 EnumValue -Enum(mips_arch_opt_value) String(20kc) Value(88) Canonical +Enum(mips_arch_opt_value) String(5kf) Value(89) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(r20kc) Value(88) +Enum(mips_arch_opt_value) String(r5kf) Value(89) =20 EnumValue -Enum(mips_arch_opt_value) String(sb1) Value(89) Canonical +Enum(mips_arch_opt_value) String(20kc) Value(90) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(sb1a) Value(90) Canonical +Enum(mips_arch_opt_value) String(r20kc) Value(90) =20 EnumValue -Enum(mips_arch_opt_value) String(sr71000) Value(91) Canonical +Enum(mips_arch_opt_value) String(sb1) Value(91) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(sr71k) Value(91) +Enum(mips_arch_opt_value) String(sb1a) Value(92) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(xlr) Value(92) Canonical +Enum(mips_arch_opt_value) String(sr71000) Value(93) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(loongson3a) Value(93) Canonical +Enum(mips_arch_opt_value) String(sr71k) Value(93) =20 EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(94) Canonical +Enum(mips_arch_opt_value) String(xlr) Value(94) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(95) Canonical +Enum(mips_arch_opt_value) String(loongson3a) Value(95) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(96) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(96) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(97) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(97) Canonical =20 EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(98) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(98) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(octeon3) Value(99) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(xlp) Value(100) Canonical =20 diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index c32532b..c3cd52d 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1280,6 +1280,19 @@ static const struct mips_rtx_cost_data COSTS_N_INSNS (41), /* int_div_di */ 1, /* branch_cost */ 4 /* memory_latency */ + }, + { /* M5100 */ + COSTS_N_INSNS (4), /* fp_add */ + COSTS_N_INSNS (4), /* fp_mult_sf */ + COSTS_N_INSNS (5), /* fp_mult_df */ + COSTS_N_INSNS (17), /* fp_div_sf */ + COSTS_N_INSNS (32), /* fp_div_df */ + COSTS_N_INSNS (5), /* int_mult_si */ + COSTS_N_INSNS (5), /* int_mult_di */ + COSTS_N_INSNS (34), /* int_div_si */ + COSTS_N_INSNS (68), /* int_div_di */ + 1, /* branch_cost */ + 4 /* memory_latency */ } }; =20 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 37f5b54..2cd365d 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -724,7 +724,7 @@ struct mips_cpu_info { %{march=3Dmips32r2|march=3Dm4k|march=3D4ke*|march=3D4ksd|march=3D24k*= \ |march=3D34k*|march=3D74k*|march=3Dm14k*|march=3D1004k*: -mips32r2}= \ %{march=3Dmips32r3: -mips32r3} \ - %{march=3Dmips32r5|march=3Dp5600: -mips32r5} \ + %{march=3Dmips32r5|march=3Dp5600|march=3Dm5100|march=3Dm5101: -mips32= r5} \ %{march=3Dmips32r6: -mips32r6} \ %{march=3Dmips64|march=3D5k*|march=3D20k*|march=3Dsb1*|march=3Dsr7100= 0 \ |march=3Dxlr: -mips64} \ @@ -748,7 +748,7 @@ struct mips_cpu_info { "%{mhard-float|msoft-float|mno-float|march=3Dmips*:; \ march=3Dvr41*|march=3Dm4k|march=3D4k*|march=3D24kc|march=3D24kec \ |march=3D34kc|march=3D34kn|march=3D74kc|march=3D1004kc|march=3D5kc \ - |march=3Dm14k*|march=3Docteon|march=3Dxlr: -msoft-float; \ + |march=3Dm14k*|march=3Dm5101|march=3Docteon|march=3Dxlr: -msoft-float= ; \ march=3D*: -mhard-float}" =20 /* A spec condition that matches 32-bit options. It only works if @@ -771,7 +771,8 @@ struct mips_cpu_info { =20 /* Infer a -mnan=3D2008 setting from a -mips argument. */ #define MIPS_ISA_NAN2008_SPEC \ - "%{mnan*:;mips32r6|mips64r6:-mnan=3D2008}" + "%{mnan*:;mips32r6|mips64r6:-mnan=3D2008;march=3Dm51*: \ + %{!msoft-float:-mnan=3D2008}}" =20 #if (MIPS_ABI_DEFAULT =3D=3D ABI_O64 \ || MIPS_ABI_DEFAULT =3D=3D ABI_N32 \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index ad8ad9f..cde2b4e 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -69,6 +69,7 @@ (define_enum "processor" [ p5600 w32 w64 + m5100 ]) =20 (define_c_enum "unspec" [ @@ -1086,6 +1087,7 @@ (define_insn_reservation "ghost" 0 "nothing") =20 (include "p5600.md") +(include "m5100.md") (include "4k.md") (include "5k.md") (include "20kc.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 522e924..4531d73 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -17056,6 +17056,7 @@ The processor names are: @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, +@samp{m5100}, @samp{m5101}, @samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{octeon3}, @samp{orion}, @samp{p5600}, --=20 2.4.5