From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 78177 invoked by alias); 22 Jul 2015 12:51:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 78155 invoked by uid 89); 22 Jul 2015 12:51:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jul 2015 12:51:50 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id CAC44BFB199A5; Wed, 22 Jul 2015 13:51:45 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 22 Jul 2015 13:51:48 +0100 Received: from hhmail02.hh.imgtec.org ([::1]) by hhmail02.hh.imgtec.org ([::1]) with mapi id 14.03.0235.001; Wed, 22 Jul 2015 13:51:47 +0100 From: Robert Suchanek To: Matthew Fortune , "Catherine_Moore@mentor.com" , Prachi Godbole CC: "gcc-patches@gcc.gnu.org" Subject: RE: [PATCH, MIPS] Scheduling for M51xx core family Date: Wed, 22 Jul 2015 12:56:00 -0000 Message-ID: References: <6D39441BF12EF246A7ABCE6654B02353211EC43A@LEMAIL01.le.imgtec.org> In-Reply-To: <6D39441BF12EF246A7ABCE6654B02353211EC43A@LEMAIL01.le.imgtec.org> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-IsSubscribed: yes X-SW-Source: 2015-07/txt/msg01837.txt.bz2 Hi Matthew, > > gcc/ > > > > * config/mips/m5100.md: New file. > > * config/mips/mips-cpus.def (m5100, m5101): Define. > > * config/mips/mips-tables.opt: Regenerate. > > * config/mips/mips.c (mips_rtx_cost_data): Add costs for m5100. > > * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=3Dm5100 and > > -march=3Dm5101 to -mips32r5. > > (MIPS_ARCH_FLOAT_SPEC): Map -m5101 to -msoft-float. > > (MIPS_ISA_NAN2008_SPEC): Map -march=3Dm51* to -mnan=3D2008 if > > !-msoft-float. > > * config/mips/mips.md: Include m5100.md. > > (processor): Add m5100. > > * doc/invoke.texi (-march=3D@var{arch}): Add m5100, m5101. >=20 > OK, this looks fine. The patch committed as r226065. > I did realise while reading through this that the MIPS_ARCH_FLOAT_SPEC > is not used for and ordinary MIPS Linux compiler which seems odd but > I presume this is to make it possible to use one hard-float sysroot > for any core and emulate the FPU when not present. >=20 > I think it is probably a mistake to have put MIPS_ARCH_FLOAT_SPEC in > the mti-linux.h and android.h DRIVER_SELF_SPECS so I think they need > removing. Although we support building soft-float multilibs I don't > think they actually get used very much so leaving the selection of > soft-float down to the end user in Linux seems wise. >=20 > With the i6400 scheduler committed then we can also get rid of the w32 > and w64 placeholders that were there solely to provide an R6 processor > to use as the default processor for the generic arch options. I'll send a follow-up patch to remove the redundant bits. Regards, Robert