Re: [PATCH] RISC-V: Add vwsubu.wx C API tests

["juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>]

[-- Attachment #1: Type: text/plain, Size: 104108 bytes --]

Sorry for the wrong title, it should be add vwsubu.wv C API tests



juzhe.zhong@rivai.ai
 
From: juzhe.zhong
Date: 2023-02-07 14:17
To: gcc-patches
CC: kito.cheng; Ju-Zhe Zhong
Subject: [PATCH] RISC-V: Add vwsubu.wx C API tests
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
 
gcc/testsuite/ChangeLog:
 
        * gcc.target/riscv/rvv/base/vwsubu_wv-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c: New test.
 
---
.../gcc.target/riscv/rvv/base/vwsubu_wv-1.c   | 111 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vwsubu_wv-2.c   | 111 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vwsubu_wv-3.c   | 111 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c | 111 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c | 111 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_mu-1.c           | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_mu-2.c           | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_mu-3.c           | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_tu-1.c           | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_tu-2.c           | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_tu-3.c           | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_tum-1.c          | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_tum-2.c          | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_tum-3.c          | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_tumu-1.c         | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_tumu-2.c         | 111 ++++++++++++++++++
.../riscv/rvv/base/vwsubu_wv_tumu-3.c         | 111 ++++++++++++++++++
18 files changed, 1998 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c
new file mode 100644
index 00000000000..73d261cc78b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8(vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1(vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2(vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4(vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8(vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1(vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2(vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4(vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8(vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c
new file mode 100644
index 00000000000..9866b9b1533
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8(vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1(vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2(vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4(vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8(vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1(vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2(vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4(vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8(vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c
new file mode 100644
index 00000000000..a4db286ed97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8(vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1(vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2(vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4(vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8(vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1(vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2(vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4(vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8(vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c
new file mode 100644
index 00000000000..34dc24aadb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_m(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_m(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_m(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_m(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_m(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_m(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_m(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_m(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_m(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c
new file mode 100644
index 00000000000..abcfc4b7c64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_m(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_m(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_m(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_m(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_m(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_m(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_m(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_m(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_m(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_m(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_m(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_m(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_m(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_m(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c
new file mode 100644
index 00000000000..28d38a81aec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_m(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_m(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_m(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_m(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_m(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_m(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_m(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_m(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_m(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_m(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_m(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_m(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_m(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_m(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c
new file mode 100644
index 00000000000..ad02613d4dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c
new file mode 100644
index 00000000000..f63b57d5d23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c
new file mode 100644
index 00000000000..4c62e72141b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c
new file mode 100644
index 00000000000..5bd36f109dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c
new file mode 100644
index 00000000000..6b19c2784f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c
new file mode 100644
index 00000000000..0c2378384e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c
new file mode 100644
index 00000000000..6645e70aac6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c
new file mode 100644
index 00000000000..2f39fda0e31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c
new file mode 100644
index 00000000000..5cdec869dd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c
new file mode 100644
index 00000000000..69851b0a48a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c
new file mode 100644
index 00000000000..285a84c1ad7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c
new file mode 100644
index 00000000000..1c61045e3c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vwsubu_wv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vwsubu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vwsubu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vwsubu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vwsubu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vwsubu_wv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vwsubu_wv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vwsubu_wv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vwsubu_wv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vwsubu_wv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vwsubu_wv_u64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
-- 
2.36.1