[PATCH][MIPS] Scheduler fix for the 74k & 24k.

[Simon Dardis <Simon.Dardis@imgtec.com>]

Hello,

This patch fixes a bug with the 74k & 24k schedulers. 

Back in 2006  (2ca4dfa486bd358c6e466328839977250d160393) a mips_store_data_bypass_p was added to the mips backend. Unfortunately it was defined in terms of !store_data_bypass_p, though it was correctly used for the sb1 processor pipeline descriptor at that time. Later during a code-cleanup in 2012 (e053750d33e14ca245e14e1c467709a9bf6c6282) the 24k & 74k bypasses were changed from the correct !store_data_bypass_p to !mips_store_data_bypass_p. This lead to those bypasses having inverted guard conditions.

This patch brings mips_store_data_bypass_p into line with its comments and the comments of store_data_bypass_p. It also corrects the sb1's pipeline description.
 
Thanks,
Simon

gcc/
	* config/mips/mips.c (mips_store_data_bypass_p): Bring code into
	line with comments.
	* config/mips/sb1.md: Update usage of mips_store_data_bypass_p.

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 2fe143c..23f12d1 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -13709,7 +13709,7 @@ mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
   if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
     return false;
 
-  return !store_data_bypass_p (out_insn, in_insn);
+  return store_data_bypass_p (out_insn, in_insn);
 }
 

 
diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md
index 311300e..c12fc91 100644
--- a/gcc/config/mips/sb1.md
+++ b/gcc/config/mips/sb1.md
@@ -216,7 +216,7 @@
   "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
    ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
   "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
-  "mips_store_data_bypass_p")
+  "!mips_store_data_bypass_p")
 
 ;; On SB-1, simple alu instructions can execute on the LS1 unit.
 
@@ -289,7 +289,7 @@
 (define_bypass 5
   "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
   "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
-  "mips_store_data_bypass_p")
+  "!mips_store_data_bypass_p")
 
 ;; mf{hi,lo} is 1 cycle.  
 
@@ -351,7 +351,7 @@
 (define_bypass 7
   "ir_sb1_mulsi,ir_sb1_muldi"
   "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
-  "mips_store_data_bypass_p")
+  "!mips_store_data_bypass_p")
 
 ;; The divide unit is not pipelined.  Divide busy is asserted in the 4th
 ;; cycle, and then deasserted on the latency cycle.  So only one divide at
-- 
2.1.0