From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 113517 invoked by alias); 21 Jul 2015 10:39:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 113506 invoked by uid 89); 21 Jul 2015 10:39:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 Jul 2015 10:39:02 +0000 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id BFB7F82057719 for ; Tue, 21 Jul 2015 11:38:57 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 21 Jul 2015 11:38:59 +0100 Received: from hhmail02.hh.imgtec.org ([::1]) by hhmail02.hh.imgtec.org ([::1]) with mapi id 14.03.0235.001; Tue, 21 Jul 2015 11:38:59 +0100 From: Simon Dardis To: "gcc-patches@gcc.gnu.org" Subject: [PATCH][MIPS] Scheduler fix for the 74k & 24k. Date: Tue, 21 Jul 2015 10:46:00 -0000 Message-ID: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-IsSubscribed: yes X-SW-Source: 2015-07/txt/msg01731.txt.bz2 Hello, This patch fixes a bug with the 74k & 24k schedulers.=20 Back in 2006 (2ca4dfa486bd358c6e466328839977250d160393) a mips_store_data_= bypass_p was added to the mips backend. Unfortunately it was defined in ter= ms of !store_data_bypass_p, though it was correctly used for the sb1 proces= sor pipeline descriptor at that time. Later during a code-cleanup in 2012 (= e053750d33e14ca245e14e1c467709a9bf6c6282) the 24k & 74k bypasses were chang= ed from the correct !store_data_bypass_p to !mips_store_data_bypass_p. This= lead to those bypasses having inverted guard conditions. This patch brings mips_store_data_bypass_p into line with its comments and = the comments of store_data_bypass_p. It also corrects the sb1's pipeline de= scription. =20 Thanks, Simon gcc/ * config/mips/mips.c (mips_store_data_bypass_p): Bring code into line with comments. * config/mips/sb1.md: Update usage of mips_store_data_bypass_p. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 2fe143c..23f12d1 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -13709,7 +13709,7 @@ mips_store_data_bypass_p (rtx out_insn, rtx in_insn) if (GET_CODE (PATTERN (in_insn)) =3D=3D UNSPEC_VOLATILE) return false; =20 - return !store_data_bypass_p (out_insn, in_insn); + return store_data_bypass_p (out_insn, in_insn); } =20 =20 diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md index 311300e..c12fc91 100644 --- a/gcc/config/mips/sb1.md +++ b/gcc/config/mips/sb1.md @@ -216,7 +216,7 @@ "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp" "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" - "mips_store_data_bypass_p") + "!mips_store_data_bypass_p") =20 ;; On SB-1, simple alu instructions can execute on the LS1 unit. =20 @@ -289,7 +289,7 @@ (define_bypass 5 "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" - "mips_store_data_bypass_p") + "!mips_store_data_bypass_p") =20 ;; mf{hi,lo} is 1 cycle.=20=20 =20 @@ -351,7 +351,7 @@ (define_bypass 7 "ir_sb1_mulsi,ir_sb1_muldi" "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" - "mips_store_data_bypass_p") + "!mips_store_data_bypass_p") =20 ;; The divide unit is not pipelined. Divide busy is asserted in the 4th ;; cycle, and then deasserted on the latency cycle. So only one divide at --=20 2.1.0