From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 26894 invoked by alias); 9 Jun 2011 18:34:50 -0000 Received: (qmail 26512 invoked by uid 22791); 9 Jun 2011 18:34:49 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,RFC_ABUSE_POST X-Spam-Check-By: sourceware.org Received: from mail-ew0-f47.google.com (HELO mail-ew0-f47.google.com) (209.85.215.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 09 Jun 2011 18:34:32 +0000 Received: by ewy5 with SMTP id 5so736318ewy.20 for ; Thu, 09 Jun 2011 11:34:31 -0700 (PDT) Received: by 10.14.25.144 with SMTP id z16mr539699eez.61.1307644471291; Thu, 09 Jun 2011 11:34:31 -0700 (PDT) MIME-Version: 1.0 Received: by 10.14.186.16 with HTTP; Thu, 9 Jun 2011 11:34:11 -0700 (PDT) In-Reply-To: <4DF0FAB5.6070704@gjlay.de> References: <4DF0FAB5.6070704@gjlay.de> From: Denis Chertykov Date: Thu, 09 Jun 2011 18:50:00 -0000 Message-ID: Subject: Re: [Patch, AVR]: Fix PR46779 To: Georg-Johann Lay Cc: gcc-patches@gcc.gnu.org, Anatoly Sokolov , "Eric B. Weddington" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-06/txt/msg00755.txt.bz2 2011/6/9 Georg-Johann Lay : > This is a tentative patch to fix PR46779 and hopefully also related > issues like PR45291. > - =C2=A0/* Disallow QImode in stack pointer regs. =C2=A0*/ - =C2=A0if ((regno =3D=3D REG_SP || regno =3D=3D (REG_SP + 1)) && mode =3D= =3D QImode) + =C2=A0/* Don't allocate data to non-GENERAL_REGS registers. =C2=A0*/ + + =C2=A0if (regno >=3D 32) =C2=A0 =C2=A0 =C2=A0return 0; I think that we not need in this code. GCC core must bother about this. + + =C2=A0if (GET_MODE_SIZE (mode) =3D=3D 1) =C2=A0 =C2=A0 =C2=A0return 1; I'm agree with this. + + =C2=A0/* Disallow big registers that overlap the frame pointer. + =C2=A0 =C2=A0 This will hopefully reduce the number of spill failures. = =C2=A0*/ + + =C2=A0if (GET_MODE_SIZE (mode) > 2 + =C2=A0 =C2=A0 =C2=A0&& regno <=3D REG_Y + =C2=A0 =C2=A0 =C2=A0&& regno + GET_MODE_SIZE (mode) >=3D REG_Y + 1) + =C2=A0 =C2=A0{ + =C2=A0 =C2=A0 =C2=A0return 0; + =C2=A0 =C2=A0} Fragment from GCC info: -------------------------------------- HARD_REGNO_MODE_OK (regno,=C2=A0mode)A C expression that is nonzero if it is permissible to store a value of mode=C2=A0mode=C2=A0in hard register num= ber regno=C2=A0(or in=C2=A0several registers starting with that one). For a mac= hine where all registers are equivalent, a suitable definition is #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 You need not include code to check for the numbers of fixed registers, because the allocation mechanism considers them to be always occupied. ----------------------------------------- Again, GCC core must bother about this. - =C2=A0/* Otherwise disallow all regno/mode combinations that span r28:r29= . =C2=A0*/ - =C2=A0if (regno <=3D (REG_Y + 1) && (regno + GET_MODE_SIZE (mode)) >=3D (= REG_Y + 1)) - =C2=A0 =C2=A0return 0; - - =C2=A0if (mode =3D=3D QImode) - =C2=A0 =C2=A0return 1; - - =C2=A0/* Modes larger than QImode occupy consecutive registers. =C2=A0*/ - =C2=A0if (regno + GET_MODE_SIZE (mode) > FIRST_PSEUDO_REGISTER) - =C2=A0 =C2=A0return 0; - This is a right change. Denis.