From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22224 invoked by alias); 9 Jun 2011 19:43:58 -0000 Received: (qmail 22214 invoked by uid 22791); 9 Jun 2011 19:43:57 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,RFC_ABUSE_POST X-Spam-Check-By: sourceware.org Received: from mail-ew0-f47.google.com (HELO mail-ew0-f47.google.com) (209.85.215.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 09 Jun 2011 19:43:41 +0000 Received: by ewy5 with SMTP id 5so761773ewy.20 for ; Thu, 09 Jun 2011 12:43:40 -0700 (PDT) Received: by 10.14.18.100 with SMTP id k76mr539274eek.125.1307648620177; Thu, 09 Jun 2011 12:43:40 -0700 (PDT) MIME-Version: 1.0 Received: by 10.14.186.16 with HTTP; Thu, 9 Jun 2011 12:43:19 -0700 (PDT) In-Reply-To: <4DF11D20.4030907@gjlay.de> References: <4DF0FAB5.6070704@gjlay.de> <4DF11D20.4030907@gjlay.de> From: Denis Chertykov Date: Thu, 09 Jun 2011 19:51:00 -0000 Message-ID: Subject: Re: [Patch, AVR]: Fix PR46779 To: Georg-Johann Lay Cc: gcc-patches@gcc.gnu.org, Anatoly Sokolov , "Eric B. Weddington" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-06/txt/msg00765.txt.bz2 2011/6/9 Georg-Johann Lay : > Denis Chertykov schrieb: >> 2011/6/9 Georg-Johann Lay : >>> This is a tentative patch to fix PR46779 and hopefully also related >>> issues like PR45291. >>> >> - =C2=A0/* Disallow QImode in stack pointer regs. =C2=A0*/ >> - =C2=A0if ((regno =3D=3D REG_SP || regno =3D=3D (REG_SP + 1)) && mode = =3D=3D QImode) >> + =C2=A0/* Don't allocate data to non-GENERAL_REGS registers. =C2=A0*/ >> + >> + =C2=A0if (regno >=3D 32) >> =C2=A0 =C2=A0 =C2=A0return 0; >> >> I think that we not need in this code. >> GCC core must bother about this. > > I am unsure about that. There is the "q" constraint that is used for > SP. register_operand will accept SP because regno_reg_class does not > return NO_REGS for SP. So something must stop the register allocator > from allocating ordinary data to SP. I know, this is a FIXED_REGISTERS. > In the current md there is "*movhi_sp" insn prior to "*movhi" insn. > Besides that it is strongly discouraged to have more than one move > insn for one mode, not each and every place looks at insn conditions. I'm agree. May be better to rewrite it. > > Moreover, if there is an insn like > (set (reg:HI 100) > =C2=A0 =C2=A0 (reg:HI 101)) > that matches "*movhi", what will keep IRA from allocating one of the > values to SP, i.e. chose alternative "q,r" or "r,q"? FIXED_REGISTERS. >> + =C2=A0 =C2=A0{ >> + =C2=A0 =C2=A0 =C2=A0return 0; >> + =C2=A0 =C2=A0} >> >> Fragment from GCC info: >> -------------------------------------- >> HARD_REGNO_MODE_OK (regno, mode)A C expression that is nonzero if it >> is permissible to store a value of mode mode in hard register number >> regno (or in several registers starting with that one). For a machine >> where all registers are equivalent, a suitable definition is >> >> #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 >> >> You need not include code to check for the numbers of fixed registers, >> because the allocation mechanism considers them to be always occupied. >> ----------------------------------------- >> Again, GCC core must bother about this. > > I agree with you. However, I think that the risk of spill failure > should be minimized. I have no idea how to fix a splill failure like > the following that occurs in testsuite (with -Os, no matter if the > patch is applied or not): > > ./gcc/testsuite/gcc.c-torture/execute/pr38051.c:189:1: error: unable > to find a register to spill in class 'POINTER_REGS' > ./gcc/testsuite/gcc.c-torture/execute/pr38051.c:189:1: error: this is > the insn: > (insn 61 60 62 10 (set (reg/v:SI 12 r12 [orig:73 b0 ] [73]) > =C2=A0 =C2=A0 =C2=A0 =C2=A0(mem:SI (subreg:HI (reg/v:SI 70 [ srcp2 ]) 0) = [2 *D.2218_56+0 > S4 A8])) ./gcc/testsuite/gcc.c-torture/execute/pr38051.c:64 12 {*movsi} > =C2=A0 =C2=A0 (nil)) > ./gcc/testsuite/gcc.c-torture/execute/pr38051.c:189:1: internal > compiler error: in spill_failure, at reload1.c:2113 > > Actually I have no idea if the snip in avr_hard_regno_mode_ok actually > would reduce the risk of spill failure :-/ I think, no. I will try to debug reload for pr38051.c (It will be a long process 1-2 wee= ks) Denis.