From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15407 invoked by alias); 25 May 2011 14:42:47 -0000 Received: (qmail 15399 invoked by uid 22791); 25 May 2011 14:42:46 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,RFC_ABUSE_POST,TW_OV,TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-qy0-f182.google.com (HELO mail-qy0-f182.google.com) (209.85.216.182) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 25 May 2011 14:42:32 +0000 Received: by qyk27 with SMTP id 27so4653703qyk.20 for ; Wed, 25 May 2011 07:42:32 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.20.210 with SMTP id g18mr3821684qcb.115.1306334551938; Wed, 25 May 2011 07:42:31 -0700 (PDT) Received: by 10.229.11.143 with HTTP; Wed, 25 May 2011 07:42:31 -0700 (PDT) In-Reply-To: References: <20110524155424.GA7400@intel.com> Date: Wed, 25 May 2011 15:10:00 -0000 Message-ID: Subject: Re: PATCH: PR target/49142: Invalid 8bit register operand From: "H.J. Lu" To: Uros Bizjak Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-05/txt/msg01868.txt.bz2 On Wed, May 25, 2011 at 7:00 AM, Uros Bizjak wrote: > On Tue, May 24, 2011 at 5:54 PM, H.J. Lu wrote: >> Hi, >> >> We are working on a new optimization, which turns off TARGET_MOVX. >> GCC generates: >> >> movb %ah, %dil >> >> But %ah can only be used with %[abcd][hl]. =A0This patch adds QIreg_oper= and >> and uses it in *movqi_extv_1_rex64/*movqi_extzv_2_rex64. =A0OK for trunk >> if there is no regression? > > If this is the case, then please change "q_regs_operand" predicate to > accept just QI_REG_P registers. > I thought about it. It is a problem only with %[abcd]h. I am not sure if changing q_regs_operand to accept just QI_REG_P registers will negatively impact (define_peephole2 [(set (reg FLAGS_REG) (match_operand 0 "" "")) (set (match_operand:QI 1 "register_operand" "") (match_operator:QI 2 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)])) (set (match_operand 3 "q_regs_operand" "") (zero_extend (match_dup 1)))] "(peep2_reg_dead_p (3, operands[1]) || operands_match_p (operands[1], operands[3])) && ! reg_overlap_mentioned_p (operands[3], operands[0])" [(set (match_dup 4) (match_dup 0)) (set (strict_low_part (match_dup 5)) (match_dup 2))] (define_peephole2 [(set (reg FLAGS_REG) (match_operand 0 "" "")) (set (match_operand:QI 1 "register_operand" "") (match_operator:QI 2 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)])) (parallel [(set (match_operand 3 "q_regs_operand" "") (zero_extend (match_dup 1))) (clobber (reg:CC FLAGS_REG))])] "(peep2_reg_dead_p (3, operands[1]) || operands_match_p (operands[1], operands[3])) && ! reg_overlap_mentioned_p (operands[3], operands[0])" [(set (match_dup 4) (match_dup 0)) (set (strict_low_part (match_dup 5)) (match_dup 2))] --=20 H.J.