Re: Ping: Make 128 bits the default vector size for NEON

[Ira Rosen <ira.rosen@linaro.org>]

On 6 May 2011 13:29, Richard Earnshaw <rearnsha@arm.com> wrote:
>
> On Thu, 2011-04-21 at 09:02 +0300, Ira Rosen wrote:
>> http://gcc.gnu.org/ml/gcc-patches/2011-03/msg02172.html
>>
>> The last version:
>>
>> ChangeLog:
>>
>>      * doc/invoke.texi (preferred-vector-size): Document.
>>      * params.h (PREFERRED_VECTOR_SIZE): Define.
>>      * config/arm/arm.c (arm_preferred_simd_mode): Use param
>>      PREFERRED_VECTOR_SIZE instead of
>>      TARGET_NEON_VECTORIZE_QUAD. Make 128 bits the default.
>>      (arm_autovectorize_vector_sizes): Likewise.
>>      * config/arm/arm.opt (NEON_VECTORIZE_QUAD): Add
>>      RejectNegative.
>>      * params.def (PARAM_PREFERRED_VECTOR_SIZE): Define.
>>
>> testsuite/ChangeLog:
>>
>>      * lib/target-supports.exp (check_effective_target_vect_multiple_sizes):
>>      New procedure.
>>      (add_options_for_quad_vectors): Replace with ...
>>      (add_options_for_double_vectors): ... this.
>>      * gfortran.dg/vect/pr19049.f90: Expect more printings on targets that
>>      support multiple vector sizes since the vectorizer attempts to
>>      vectorize with both vector sizes.
>>      * gcc.dg/vect/slp-reduc-6.c, gcc.dg/vect/no-vfa-vect-79.c,
>>      gcc.dg/vect/no-vfa-vect-102a.c, gcc.dg/vect/vect-outer-1a.c,
>>      gcc.dg/vect/vect-outer-1b.c, gcc.dg/vect/vect-outer-2b.c,
>>      gcc.dg/vect/vect-outer-3a.c, gcc.dg/vect/no-vfa-vect-37.c,
>>      gcc.dg/vect/vect-outer-3b.c, gcc.dg/vect/no-vfa-vect-101.c,
>>      gcc.dg/vect/no-vfa-vect-102.c, gcc.dg/vect/vect-reduc-dot-s8b.c,
>>      gcc.dg/vect/vect-outer-1.c, gcc.dg/vect/vect-104.c: Likewise.
>>      * gcc.dg/vect/vect-16.c: Rename to...
>>      * gcc.dg/vect/no-fast-math-vect-16.c: ... this to ensure that it runs
>>      without -ffast-math.
>>      * gcc.dg/vect/vect-42.c: Run with 64 bit vectors if applicable.
>>      * gcc.dg/vect/vect-multitypes-6.c, gcc.dg/vect/vect-52.c,
>>      gcc.dg/vect/vect-54.c, gcc.dg/vect/vect-46.c, gcc.dg/vect/vect-48.c,
>>      gcc.dg/vect/vect-96.c, gcc.dg/vect/vect-multitypes-3.c,
>>      gcc.dg/vect/vect-40.c: Likewise.
>>      * gcc.dg/vect/vect-outer-5.c: Remove quad-vectors option as
>>      redundant.
>>      * gcc.dg/vect/vect-109.c, gcc.dg/vect/vect-peel-1.c,
>>      gcc.dg/vect/vect-peel-2.c, gcc.dg/vect/slp-25.c,
>>      gcc.dg/vect/vect-multitypes-1.c, gcc.dg/vect/slp-3.c,
>>      gcc.dg/vect/no-vfa-pr29145.c, gcc.dg/vect/vect-multitypes-4.c:
>>      Likewise.
>>      * gcc.dg/vect/vect.exp: Run no-fast-math-vect*.c tests with
>>      -fno-fast-math.
>>
>> Thanks,
>> Ira
>
> +@item preferred-vector-size
> +Preferred vector size in bits for targets that support multiple vector sizes.
> +Invalid values are ignored.  The default is 128.
> +
>
> Shouldn't the preferred size be the largest size supported by the
> target?  Setting it to 128 might be OK today, but who knows what might
> happen in future?

How about ARM specific flag similar to -mprefer-avx128 (not tested)?

Thanks,
Ira

ChangeLog:

     * config/arm/arm.c (arm_preferred_simd_mode): Use
      flag_prefer_neon_double instead of
      TARGET_NEON_VECTORIZE_QUAD. Make 128 bits the default.
      (arm_autovectorize_vector_sizes): Likewise.
      * config/arm/arm.opt (NEON_VECTORIZE_QUAD): Add
      RejectNegative.
      (mprefer-neon-double): New flag.

(the testsuite part is unchanged).


Index: config/arm/arm.c
===================================================================
--- config/arm/arm.c    (revision 173546)
+++ config/arm/arm.c    (working copy)
@@ -22482,16 +22482,16 @@ arm_preferred_simd_mode (enum machine_mode mode)
     switch (mode)
       {
       case SFmode:
-       return TARGET_NEON_VECTORIZE_QUAD ? V4SFmode : V2SFmode;
-      case SImode:
-       return TARGET_NEON_VECTORIZE_QUAD ? V4SImode : V2SImode;
-      case HImode:
-       return TARGET_NEON_VECTORIZE_QUAD ? V8HImode : V4HImode;
-      case QImode:
-       return TARGET_NEON_VECTORIZE_QUAD ? V16QImode : V8QImode;
-      case DImode:
-       if (TARGET_NEON_VECTORIZE_QUAD)
-         return V2DImode;
+        return flag_prefer_neon_double ? V2SFmode : V4SFmode;
+       case SImode:
+        return flag_prefer_neon_double ? V2SImode : V4SImode;
+       case HImode:
+        return flag_prefer_neon_double ? V4HImode : V8HImode;
+       case QImode:
+        return flag_prefer_neon_double ? V8QImode : V16QImode;
+       case DImode:
+        if (!flag_prefer_neon_double)
+          return V2DImode;
        break;

       default:;
@@ -23722,7 +23722,7 @@ arm_expand_sync (enum machine_mode mode,
 static unsigned int
 arm_autovectorize_vector_sizes (void)
 {
-  return TARGET_NEON_VECTORIZE_QUAD ? 16 | 8 : 0;
+  return (!flag_prefer_neon_double) ? 16 | 8 : 0;
 }

 static bool
Index: config/arm/arm.opt
===================================================================
--- config/arm/arm.opt  (revision 173546)
+++ config/arm/arm.opt  (working copy)
@@ -160,9 +160,13 @@ Target Report RejectNegative Mask(LITTLE_WORDS)
 Assume big endian bytes, little endian words

 mvectorize-with-neon-quad
-Target Report Mask(NEON_VECTORIZE_QUAD)
+Target Report RejectNegative Mask(NEON_VECTORIZE_QUAD)
 Use Neon quad-word (rather than double-word) registers for vectorization

+mprefer-neon-double
+Target Report Var(flag_prefer_neon_double) Init(0)
+Use Neon double-word registers for vectorization
+
 mword-relocations
 Target Report Var(target_word_relocations)
Init(TARGET_DEFAULT_WORD_RELOCATIONS)
 Only generate absolute relocations on word sized values.




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