From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2928 invoked by alias); 8 May 2011 10:57:02 -0000 Received: (qmail 2911 invoked by uid 22791); 8 May 2011 10:57:00 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,TW_AV X-Spam-Check-By: sourceware.org Received: from mail-yx0-f175.google.com (HELO mail-yx0-f175.google.com) (209.85.213.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 08 May 2011 10:56:45 +0000 Received: by yxn22 with SMTP id 22so1896247yxn.20 for ; Sun, 08 May 2011 03:56:44 -0700 (PDT) MIME-Version: 1.0 Received: by 10.151.28.19 with SMTP id f19mr5184441ybj.233.1304852202909; Sun, 08 May 2011 03:56:42 -0700 (PDT) Received: by 10.150.218.7 with HTTP; Sun, 8 May 2011 03:56:42 -0700 (PDT) In-Reply-To: <1304677756.5165.16.camel@e102346-lin.cambridge.arm.com> References: <1304677756.5165.16.camel@e102346-lin.cambridge.arm.com> Date: Sun, 08 May 2011 13:42:00 -0000 Message-ID: Subject: Re: Ping: Make 128 bits the default vector size for NEON From: Ira Rosen To: Richard Earnshaw Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-05/txt/msg00609.txt.bz2 On 6 May 2011 13:29, Richard Earnshaw wrote: > > On Thu, 2011-04-21 at 09:02 +0300, Ira Rosen wrote: >> http://gcc.gnu.org/ml/gcc-patches/2011-03/msg02172.html >> >> The last version: >> >> ChangeLog: >> >> =A0 =A0 =A0* doc/invoke.texi (preferred-vector-size): Document. >> =A0 =A0 =A0* params.h (PREFERRED_VECTOR_SIZE): Define. >> =A0 =A0 =A0* config/arm/arm.c (arm_preferred_simd_mode): Use param >> =A0 =A0 =A0PREFERRED_VECTOR_SIZE instead of >> =A0 =A0 =A0TARGET_NEON_VECTORIZE_QUAD. Make 128 bits the default. >> =A0 =A0 =A0(arm_autovectorize_vector_sizes): Likewise. >> =A0 =A0 =A0* config/arm/arm.opt (NEON_VECTORIZE_QUAD): Add >> =A0 =A0 =A0RejectNegative. >> =A0 =A0 =A0* params.def (PARAM_PREFERRED_VECTOR_SIZE): Define. >> >> testsuite/ChangeLog: >> >> =A0 =A0 =A0* lib/target-supports.exp (check_effective_target_vect_multip= le_sizes): >> =A0 =A0 =A0New procedure. >> =A0 =A0 =A0(add_options_for_quad_vectors): Replace with ... >> =A0 =A0 =A0(add_options_for_double_vectors): ... this. >> =A0 =A0 =A0* gfortran.dg/vect/pr19049.f90: Expect more printings on targ= ets that >> =A0 =A0 =A0support multiple vector sizes since the vectorizer attempts to >> =A0 =A0 =A0vectorize with both vector sizes. >> =A0 =A0 =A0* gcc.dg/vect/slp-reduc-6.c, gcc.dg/vect/no-vfa-vect-79.c, >> =A0 =A0 =A0gcc.dg/vect/no-vfa-vect-102a.c, gcc.dg/vect/vect-outer-1a.c, >> =A0 =A0 =A0gcc.dg/vect/vect-outer-1b.c, gcc.dg/vect/vect-outer-2b.c, >> =A0 =A0 =A0gcc.dg/vect/vect-outer-3a.c, gcc.dg/vect/no-vfa-vect-37.c, >> =A0 =A0 =A0gcc.dg/vect/vect-outer-3b.c, gcc.dg/vect/no-vfa-vect-101.c, >> =A0 =A0 =A0gcc.dg/vect/no-vfa-vect-102.c, gcc.dg/vect/vect-reduc-dot-s8b= .c, >> =A0 =A0 =A0gcc.dg/vect/vect-outer-1.c, gcc.dg/vect/vect-104.c: Likewise. >> =A0 =A0 =A0* gcc.dg/vect/vect-16.c: Rename to... >> =A0 =A0 =A0* gcc.dg/vect/no-fast-math-vect-16.c: ... this to ensure that= it runs >> =A0 =A0 =A0without -ffast-math. >> =A0 =A0 =A0* gcc.dg/vect/vect-42.c: Run with 64 bit vectors if applicabl= e. >> =A0 =A0 =A0* gcc.dg/vect/vect-multitypes-6.c, gcc.dg/vect/vect-52.c, >> =A0 =A0 =A0gcc.dg/vect/vect-54.c, gcc.dg/vect/vect-46.c, gcc.dg/vect/vec= t-48.c, >> =A0 =A0 =A0gcc.dg/vect/vect-96.c, gcc.dg/vect/vect-multitypes-3.c, >> =A0 =A0 =A0gcc.dg/vect/vect-40.c: Likewise. >> =A0 =A0 =A0* gcc.dg/vect/vect-outer-5.c: Remove quad-vectors option as >> =A0 =A0 =A0redundant. >> =A0 =A0 =A0* gcc.dg/vect/vect-109.c, gcc.dg/vect/vect-peel-1.c, >> =A0 =A0 =A0gcc.dg/vect/vect-peel-2.c, gcc.dg/vect/slp-25.c, >> =A0 =A0 =A0gcc.dg/vect/vect-multitypes-1.c, gcc.dg/vect/slp-3.c, >> =A0 =A0 =A0gcc.dg/vect/no-vfa-pr29145.c, gcc.dg/vect/vect-multitypes-4.c: >> =A0 =A0 =A0Likewise. >> =A0 =A0 =A0* gcc.dg/vect/vect.exp: Run no-fast-math-vect*.c tests with >> =A0 =A0 =A0-fno-fast-math. >> >> Thanks, >> Ira > > +@item preferred-vector-size > +Preferred vector size in bits for targets that support multiple vector s= izes. > +Invalid values are ignored. =A0The default is 128. > + > > Shouldn't the preferred size be the largest size supported by the > target? =A0Setting it to 128 might be OK today, but who knows what might > happen in future? How about ARM specific flag similar to -mprefer-avx128 (not tested)? Thanks, Ira ChangeLog: * config/arm/arm.c (arm_preferred_simd_mode): Use flag_prefer_neon_double instead of TARGET_NEON_VECTORIZE_QUAD. Make 128 bits the default. (arm_autovectorize_vector_sizes): Likewise. * config/arm/arm.opt (NEON_VECTORIZE_QUAD): Add RejectNegative. (mprefer-neon-double): New flag. (the testsuite part is unchanged). Index: config/arm/arm.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- config/arm/arm.c (revision 173546) +++ config/arm/arm.c (working copy) @@ -22482,16 +22482,16 @@ arm_preferred_simd_mode (enum machine_mode mode) switch (mode) { case SFmode: - return TARGET_NEON_VECTORIZE_QUAD ? V4SFmode : V2SFmode; - case SImode: - return TARGET_NEON_VECTORIZE_QUAD ? V4SImode : V2SImode; - case HImode: - return TARGET_NEON_VECTORIZE_QUAD ? V8HImode : V4HImode; - case QImode: - return TARGET_NEON_VECTORIZE_QUAD ? V16QImode : V8QImode; - case DImode: - if (TARGET_NEON_VECTORIZE_QUAD) - return V2DImode; + return flag_prefer_neon_double ? V2SFmode : V4SFmode; + case SImode: + return flag_prefer_neon_double ? V2SImode : V4SImode; + case HImode: + return flag_prefer_neon_double ? V4HImode : V8HImode; + case QImode: + return flag_prefer_neon_double ? V8QImode : V16QImode; + case DImode: + if (!flag_prefer_neon_double) + return V2DImode; break; default:; @@ -23722,7 +23722,7 @@ arm_expand_sync (enum machine_mode mode, static unsigned int arm_autovectorize_vector_sizes (void) { - return TARGET_NEON_VECTORIZE_QUAD ? 16 | 8 : 0; + return (!flag_prefer_neon_double) ? 16 | 8 : 0; } static bool Index: config/arm/arm.opt =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- config/arm/arm.opt (revision 173546) +++ config/arm/arm.opt (working copy) @@ -160,9 +160,13 @@ Target Report RejectNegative Mask(LITTLE_WORDS) Assume big endian bytes, little endian words mvectorize-with-neon-quad -Target Report Mask(NEON_VECTORIZE_QUAD) +Target Report RejectNegative Mask(NEON_VECTORIZE_QUAD) Use Neon quad-word (rather than double-word) registers for vectorization +mprefer-neon-double +Target Report Var(flag_prefer_neon_double) Init(0) +Use Neon double-word registers for vectorization + mword-relocations Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) Only generate absolute relocations on word sized values. > > R. > > >