From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22137 invoked by alias); 1 Apr 2011 06:57:38 -0000 Received: (qmail 21727 invoked by uid 22791); 1 Apr 2011 06:57:35 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_PASS,TW_QE,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from smtp-out.google.com (HELO smtp-out.google.com) (74.125.121.67) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 01 Apr 2011 06:57:29 +0000 Received: from kpbe18.cbf.corp.google.com (kpbe18.cbf.corp.google.com [172.25.105.82]) by smtp-out.google.com with ESMTP id p316vRjI023654 for ; Thu, 31 Mar 2011 23:57:27 -0700 Received: from ywi6 (ywi6.prod.google.com [10.192.9.6]) by kpbe18.cbf.corp.google.com with ESMTP id p316vPrx005482 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NOT) for ; Thu, 31 Mar 2011 23:57:26 -0700 Received: by ywi6 with SMTP id 6so1466624ywi.31 for ; Thu, 31 Mar 2011 23:57:25 -0700 (PDT) MIME-Version: 1.0 Received: by 10.150.74.13 with SMTP id w13mr3886952yba.313.1301641045462; Thu, 31 Mar 2011 23:57:25 -0700 (PDT) Received: by 10.150.189.20 with HTTP; Thu, 31 Mar 2011 23:57:25 -0700 (PDT) In-Reply-To: <4D94A47C.5070305@linaro.org> References: <4D925EA7.2080102@linaro.org> <4D94A47C.5070305@linaro.org> Date: Fri, 01 Apr 2011 06:57:00 -0000 Message-ID: Subject: Re: [PATCH, ARM] PR47855 Compute attr "length" for some thumb2 insns From: Carrot Wei To: Ramana Radhakrishnan Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-System-Of-Record: true X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-04/txt/msg00011.txt.bz2 Hi Ramana On Thu, Mar 31, 2011 at 11:57 PM, Ramana Radhakrishnan wrote: >>> Hi Carrot, >>> =A0 =A0 =A0 =A0How about adding an alternative only enabled for T2 that= uses the >>> `l' >>> constraint and inventing new constraints for some of the constant values >>> that are valid for 16 bit instructions since the `I' and `L' constraints >>> have different meanings depending on whether TARGET_32BIT is valid or n= ot >>> ? >>> We could then set the value of the length attribute accordingly. I don't >>> think we can change the meaning of the I and L constraints very easily >>> given >>> the amount of churn that might be needed >>> >> You are right. Now the logic is much clearer by splitting the constraint= s. > > Sorry I wasn't too clear . > > What I meant was to use the "enabled" trick and enable this only when Thu= mb2 > is enabled in the compiler. > > So what you could do instead is add the alternative and then use the arch > attribute to enable this only for Thumb2. > > i.e. > >>> =A0(define_insn "*arm_cmpsi_insn" >>> =A0 =A0[(set (reg:CC CC_REGNUM) >>> - =A0 =A0 =A0 (compare:CC (match_operand:SI 0 "s_register_operand" "r,r= ") >>> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (match_operand:SI 1 "arm_add_oper= and" =A0 =A0"rI,L")))] >>> + =A0 =A0 =A0 (compare:CC (match_operand:SI 0 "s_register_operand" "l,r= ,r,r") >>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (match_operand:SI 1 "arm_add_oper= and" >>> =A0"Py,r,I,L")))] >>> =A0 =A0"TARGET_32BIT" >>> =A0 =A0"@ >>> =A0 =A0 cmp%?\\t%0, %1 >>> + =A0 cmp%?\\t%0, %1 >>> + =A0 cmp%?\\t%0, %1 >>> =A0 =A0 cmn%?\\t%0, #%n1" >>> - =A0[(set_attr "conds" "set")] >>> + =A0[(set_attr "conds" "set") > > =A0 =A0 =A0 (set_attr "arch" "t2, any") > =A0 =A0 =A0 (set_attr "length" "2, 4")] > > Does that look any better ? That way you can now safely add options on a = per > arch basis and reduce the amount of complexity for some of these length > calculations. > Thank you for the knowledge, this is the first time I see an usage of attribute "arch". I modified the pattern by enabling the new alternatives for thumb2 only and= set attribute "length" accordingly. The patch was tested on arm qemu without regression, OK for install? thanks Carrot ChangeLog: 2011-04-01 Wei Guozhi PR target/47855 * config/arm/arm.md (arm_cmpsi_insn): Compute attr "length". (arm_cond_branch): Likewise. (arm_cond_branch_reversed): Likewise. (arm_jump): Likewise. (push_multi): Likewise. * config/arm/constraints.md (Py): New constraint. Index: constraints.md =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- constraints.md (revision 171337) +++ constraints.md (working copy) @@ -31,7 +31,7 @@ ;; The following multi-letter normal constraints have been used: ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz ;; in Thumb-1 state: Pa, Pb, Pc, Pd -;; in Thumb-2 state: Ps, Pt, Pu, Pv, Pw, Px +;; in Thumb-2 state: Ps, Pt, Pu, Pv, Pw, Px, Py ;; The following memory constraints have been used: ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us @@ -189,6 +189,11 @@ (and (match_code "const_int") (match_test "TARGET_THUMB2 && ival >=3D -7 && ival <=3D -1"))) +(define_constraint "Py" + "@internal In Thumb-2 state a constant in the range 0 to 255" + (and (match_code "const_int") + (match_test "TARGET_THUMB2 && ival >=3D 0 && ival <=3D 255"))) + (define_constraint "G" "In ARM/Thumb-2 state a valid FPA immediate constant." (and (match_code "const_double") Index: arm.md =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- arm.md (revision 171337) +++ arm.md (working copy) @@ -7109,13 +7109,17 @@ (define_insn "*arm_cmpsi_insn" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 0 "s_register_operand" "r,r") - (match_operand:SI 1 "arm_add_operand" "rI,L")))] + (compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r") + (match_operand:SI 1 "arm_add_operand" "Py,r,rI,L")))] "TARGET_32BIT" "@ cmp%?\\t%0, %1 + cmp%?\\t%0, %1 + cmp%?\\t%0, %1 cmn%?\\t%0, #%n1" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "arch" "t2,t2,any,any") + (set_attr "length" "2,2,4,4")] ) (define_insn "*cmpsi_shiftsi" @@ -7286,7 +7290,14 @@ return \"b%d1\\t%l0\"; " [(set_attr "conds" "use") - (set_attr "type" "branch")] + (set_attr "type" "branch") + (set (attr "length") + (if_then_else + (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0)) + (and (ge (minus (match_dup 0) (pc)) (const_int -250)) + (le (minus (match_dup 0) (pc)) (const_int 256)))) + (const_int 2) + (const_int 4)))] ) (define_insn "*arm_cond_branch_reversed" @@ -7305,7 +7316,14 @@ return \"b%D1\\t%l0\"; " [(set_attr "conds" "use") - (set_attr "type" "branch")] + (set_attr "type" "branch") + (set (attr "length") + (if_then_else + (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0)) + (and (ge (minus (match_dup 0) (pc)) (const_int -250)) + (le (minus (match_dup 0) (pc)) (const_int 256)))) + (const_int 2) + (const_int 4)))] ) @@ -7757,7 +7775,14 @@ return \"b%?\\t%l0\"; } " - [(set_attr "predicable" "yes")] + [(set_attr "predicable" "yes") + (set (attr "length") + (if_then_else + (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0)) + (and (ge (minus (match_dup 0) (pc)) (const_int -2044)) + (le (minus (match_dup 0) (pc)) (const_int 2048)))) + (const_int 2) + (const_int 4)))] ) (define_insn "*thumb_jump" @@ -10256,7 +10281,29 @@ return \"\"; }" - [(set_attr "type" "store4")] + [(set_attr "type" "store4") + (set (attr "length") + (if_then_else + (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0)) + (ne (symbol_ref "{ + /* Check if there are any high register (except lr) + references in the list. KEEP the following iteration + in sync with the template above. */ + int i, regno, hi_reg; + int num_saves =3D XVECLEN (operands[2], 0); + regno =3D REGNO (operands[1]); + hi_reg =3D (REGNO_REG_CLASS (regno) =3D=3D HI_REGS) + && (regno !=3D LR_REGNUM); + for (i =3D 1; i < num_saves && !hi_reg; i++) + { + regno =3D REGNO (XEXP (XVECEXP (operands[2], 0, i), 0)); + hi_reg |=3D (REGNO_REG_CLASS (regno) =3D=3D HI_REGS) + && (regno !=3D LR_REGNUM); + } + !hi_reg; }") + (const_int 0))) + (const_int 2) + (const_int 4)))] ) (define_insn "stack_tie"