From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14703 invoked by alias); 27 Jun 2011 18:40:40 -0000 Received: (qmail 14526 invoked by uid 22791); 27 Jun 2011 18:40:37 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 27 Jun 2011 18:40:19 +0000 Received: by qwh5 with SMTP id 5so2732725qwh.20 for ; Mon, 27 Jun 2011 11:40:18 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.79.196 with SMTP id q4mr4452781qck.132.1309200018528; Mon, 27 Jun 2011 11:40:18 -0700 (PDT) Received: by 10.229.238.19 with HTTP; Mon, 27 Jun 2011 11:40:18 -0700 (PDT) In-Reply-To: <201106271828.p5RISq1L030434@d06av02.portsmouth.uk.ibm.com> References: <201106271828.p5RISq1L030434@d06av02.portsmouth.uk.ibm.com> Date: Mon, 27 Jun 2011 18:56:00 -0000 Message-ID: Subject: Re: PATCH [10/n]: Prepare x32: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const From: "H.J. Lu" To: Ulrich Weigand Cc: gcc-patches@gcc.gnu.org, bernds@codesourcery.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-06/txt/msg02045.txt.bz2 On Mon, Jun 27, 2011 at 11:28 AM, Ulrich Weigand wrot= e: > H.J. Lu wrote: >> On Mon, Jun 27, 2011 at 7:47 AM, Ulrich Weigand wr= ote: >> > The actual problem >> > here is that this part of gen_reload takes the approach to transform >> > >> > =A0out <- op0 + op1 >> > >> > into >> > >> > =A0out <- op0 >> > =A0out <- out + op1 >> > >> > which is invalid if writing to out clobbers op1. > >> The problem is reload 0 puts OP1 in OUT. Adding >> >> gcc_assert (!reg_overlap_mentioned_p (out, op1)); >> >> doesn't help in reload 2. =A0How can I check if OP1 overlaps with >> OUT in previous reload? > > Sorry, I don't understand how previous reloads come into play here. > gen_reload is supposed to load "in" (which happens to be of the > form op0 + op1) into "out", which means it is of course supposed > to clobber "out" (as long as that doesn't implictly clobber op0 > or op1 before they're used). =A0Any conflicts with other reloads ought > to have been resolved earlier. > > Can you elaborate? > Here is the output from reload: Reloads for insn # 588 Reload 0: reload_in (DI) =3D (reg/v/f:DI 182 [ b ]) GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum =3D 0) reload_in_reg: (reg/v/f:DI 182 [ b ]) reload_reg_rtx: (reg:DI 1 dx) Reload 1: reload_in (DI) =3D (zero_extend:DI (plus:SI (subreg:SI (reg/v/f:D= I 182 [ b ]) 0) (const_int 8 [0x8])= )) GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum =3D 0) reload_in_reg: (zero_extend:DI (plus:SI (subreg:SI (reg/v/f:DI 182 = [ b ]) 0) (const_int 8 [0x8])= )) reload_reg_rtx: (reg:DI 1 dx) Reload 2: reload_out (DF) =3D (mem:DF (zero_extend:DI (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) (const_int 8 [0x8]))) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset: 0B]+0 S8 A64]) NO_REGS, RELOAD_FOR_OUTPUT (opnum =3D 0), optional reload_out_reg: (mem:DF (zero_extend:DI (plus:SI (subreg:SI (reg/v/= f:DI 182 [ b ]) 0) (const_int 8 [0x8]))) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset: 0B]+0 S8 A64]) leads to (insn 1017 587 1020 34 (set (reg:DI 1 dx) (mem/c:DI (plus:DI (reg/f:DI 7 sp) (const_int 112 [0x70])) [5 %sfp+-208 S8 A64])) spooles.c:29= 1 62 {*movdi_internal_rex64} (nil)) (insn 1020 1017 1022 34 (set (reg:SI 1 dx) (const_int 8 [0x8])) spooles.c:291 64 {*movsi_internal} (nil)) (insn 1022 1020 1023 34 (set (reg:SI 1 dx) (reg:SI 1 dx)) spooles.c:291 64 {*movsi_internal} (nil)) (insn 1023 1022 1024 34 (set (reg:SI 1 dx) (plus:SI (reg:SI 1 dx) (const_int 8 [0x8]))) spooles.c:291 248 {*lea_1_x32} (expr_list:REG_EQUIV (plus:SI (subreg:SI (reg:DI 1 dx) 0) (const_int 8 [0x8])) (nil))) (insn 1024 1023 588 34 (set (reg:DI 1 dx) (zero_extend:DI (reg:SI 1 dx))) spooles.c:291 112 {*zero_extendsidi2_rex64} (expr_list:REG_EQUIV (zero_extend:DI (plus:SI (subreg:SI (reg:DI 1 dx)= 0) (const_int 8 [0x8]))) (nil))) (insn 588 1024 589 34 (set (mem:DF (reg:DI 1 dx) [4 MEM[base: b_96(D), inde= x: D.15020_278, step: 8, offset: 0B]+0 S8 A64]) (reg:DF 0 ax [orig:340 D.14980 ] [340])) spooles.c:291 106 {*movdf_internal_rex64} (nil)) Reload 0 puts (reg/v/f:DI 182 [ b ]) in (reg:DI 1 dx) for input. However, reload 2 puts (reg/v/f:DI 182 [ b ]) in (reg:DI 1 dx) for output.without checking w= hat reload 0 did. --=20 H.J.