From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29717 invoked by alias); 19 Apr 2011 11:18:30 -0000 Received: (qmail 29704 invoked by uid 22791); 19 Apr 2011 11:18:29 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,RFC_ABUSE_POST X-Spam-Check-By: sourceware.org Received: from mail-ey0-f175.google.com (HELO mail-ey0-f175.google.com) (209.85.215.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 19 Apr 2011 11:18:09 +0000 Received: by eye27 with SMTP id 27so1852656eye.20 for ; Tue, 19 Apr 2011 04:18:08 -0700 (PDT) Received: by 10.213.0.206 with SMTP id 14mr2618611ebc.4.1303211888100; Tue, 19 Apr 2011 04:18:08 -0700 (PDT) MIME-Version: 1.0 Received: by 10.213.27.144 with HTTP; Tue, 19 Apr 2011 04:17:48 -0700 (PDT) In-Reply-To: <4DAD61D9.6020209@gjlay.de> References: <4DA6CB8E.1040707@gjlay.de> <4DA72CC6.5030001@gjlay.de> <4DA880F6.4070109@gjlay.de> <4DAC14F0.5070304@gjlay.de> <4DAD521B.9020501@gjlay.de> <4DAD61D9.6020209@gjlay.de> From: Denis Chertykov Date: Tue, 19 Apr 2011 12:07:00 -0000 Message-ID: Subject: Re: [Patch,AVR]: FIX ICE in optabs due to bad rotate expander. To: Georg-Johann Lay Cc: gcc-patches@gcc.gnu.org, Anatoly Sokolov , Eric Weddington Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-04/txt/msg01515.txt.bz2 2011/4/19 Georg-Johann Lay : > Denis Chertykov schrieb: >> 2011/4/19 Georg-Johann Lay : >>> How can add, sub etc. be split? This would need an explicit >>> representation of carry. >> >> Yes. >> >> Look at http://gcc.gnu.org/ml/gcc/2005-03/msg00871.html > > Just skimmed the conversation. I thought about making AVR ISA's > effects on SREG explicit several times, but I always got stuck at some > point. > > - It's not only about scheduling (which does not happen for avr) but > =C2=A0also about moving instructions across jumps. > > - Many transformations would happen before reload, but at these stages > the effect on SREG is not yet known in many cases. There is > sophisticated instruction output for many patterns, and their impact > on SREG/CC is not known before reload. > > - Making CC explicit would render many single_set insns to PARALLELs > making the optimizers' live much harder or impossible. Imagine > instructions that could be combined. Explicit CC would clutter up > insns and combine won't try to transform the bulky patterns. > > - Backend would be much more complicated, harder to maintain and > understand. Almost any insn would have to be changed. Generally, I'm agree with you, the AVR port uses CC0 because of that. Denis.