From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28853 invoked by alias); 27 Jun 2011 21:36:14 -0000 Received: (qmail 28730 invoked by uid 22791); 27 Jun 2011 21:36:12 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 27 Jun 2011 21:35:58 +0000 Received: by qwh5 with SMTP id 5so2810728qwh.20 for ; Mon, 27 Jun 2011 14:35:57 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.79.196 with SMTP id q4mr4605401qck.132.1309210556055; Mon, 27 Jun 2011 14:35:56 -0700 (PDT) Received: by 10.229.191.21 with HTTP; Mon, 27 Jun 2011 14:35:55 -0700 (PDT) In-Reply-To: References: <201106271859.p5RIxBP1013069@d06av02.portsmouth.uk.ibm.com> Date: Mon, 27 Jun 2011 22:19:00 -0000 Message-ID: Subject: Re: PATCH [10/n]: Prepare x32: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const From: "H.J. Lu" To: Ulrich Weigand Cc: gcc-patches@gcc.gnu.org, bernds@codesourcery.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-06/txt/msg02069.txt.bz2 On Mon, Jun 27, 2011 at 1:42 PM, H.J. Lu wrote: > On Mon, Jun 27, 2011 at 11:59 AM, Ulrich Weigand wr= ote: >> H.J. Lu wrote: >> >>> Reloads for insn # 588 >>> Reload 0: reload_in (DI) =3D3D (reg/v/f:DI 182 [ b ]) >>> =A0 =A0 =A0 =A0 GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum =3D3D 0) >>> =A0 =A0 =A0 =A0 reload_in_reg: (reg/v/f:DI 182 [ b ]) >>> =A0 =A0 =A0 =A0 reload_reg_rtx: (reg:DI 1 dx) >>> Reload 1: reload_in (DI) =3D3D (zero_extend:DI (plus:SI (subreg:SI (reg= /v/f:D=3D >>> I 182 >>> [ b ]) 0) >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (const_int 8 [0x8])=3D >>> )) >>> =A0 =A0 =A0 =A0 GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum =3D3D 0) >>> =A0 =A0 =A0 =A0 reload_in_reg: (zero_extend:DI (plus:SI (subreg:SI (reg= /v/f:DI 182 =3D >>> [ b >>> ]) 0) >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (const_int 8 [0x8])=3D >>> )) >>> =A0 =A0 =A0 =A0 reload_reg_rtx: (reg:DI 1 dx) >>> Reload 2: reload_out (DF) =3D3D (mem:DF (zero_extend:DI (plus:SI (subre= g:SI >>> (reg/v/f:DI 182 [ b ]) 0) >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (const_int 8 >>> [0x8]))) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset: 0B]= +0 S8 >>> A64]) >>> =A0 =A0 =A0 =A0 NO_REGS, RELOAD_FOR_OUTPUT (opnum =3D3D 0), optional >>> =A0 =A0 =A0 =A0 reload_out_reg: (mem:DF (zero_extend:DI (plus:SI (subre= g:SI (reg/v/=3D >>> f:DI >>> 182 [ b ]) 0) >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (const_int 8 >>> [0x8]))) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset: 0B]= +0 S8 >>> A64]) >>> >>> leads to >>> >> >>> (insn 1017 587 1020 34 (set (reg:DI 1 dx) >>> =A0 =A0 =A0 =A0 (mem/c:DI (plus:DI (reg/f:DI 7 sp) >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (const_int 112 [0x70])) [5 %sfp+-208 S8= A64])) spooles.c:29=3D >>> 1 62 >>> {*movdi_internal_rex64} >>> =A0 =A0 =A0(nil)) >> >> So this is the reload insn generated from reload 0. =A0So far so good. >> >>> (insn 1020 1017 1022 34 (set (reg:SI 1 dx) >>> =A0 =A0 =A0 =A0 (const_int 8 [0x8])) spooles.c:291 64 {*movsi_internal} >>> =A0 =A0 =A0(nil)) >>> >>> (insn 1022 1020 1023 34 (set (reg:SI 1 dx) >>> =A0 =A0 =A0 =A0 (reg:SI 1 dx)) spooles.c:291 64 {*movsi_internal} >>> =A0 =A0 =A0(nil)) >>> >>> (insn 1023 1022 1024 34 (set (reg:SI 1 dx) >>> =A0 =A0 =A0 =A0 (plus:SI (reg:SI 1 dx) >>> =A0 =A0 =A0 =A0 =A0 =A0 (const_int 8 [0x8]))) spooles.c:291 248 {*lea_1= _x32} >>> =A0 =A0 =A0(expr_list:REG_EQUIV (plus:SI (subreg:SI (reg:DI 1 dx) 0) >>> =A0 =A0 =A0 =A0 =A0 =A0 (const_int 8 [0x8])) >>> =A0 =A0 =A0 =A0 (nil))) >>> >>> (insn 1024 1023 588 34 (set (reg:DI 1 dx) >>> =A0 =A0 =A0 =A0 (zero_extend:DI (reg:SI 1 dx))) spooles.c:291 112 >>> {*zero_extendsidi2_rex64} >>> =A0 =A0 =A0(expr_list:REG_EQUIV (zero_extend:DI (plus:SI (subreg:SI (re= g:DI 1 dx)=3D >>> =A00) >>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (const_int 8 [0x8]))) >>> =A0 =A0 =A0 =A0 (nil))) >> >> All these reload insns are generated from reload 1. >> >>> (insn 588 1024 589 34 (set (mem:DF (reg:DI 1 dx) [4 MEM[base: b_96(D), = inde=3D >>> x: >>> D.15020_278, step: 8, offset: 0B]+0 S8 A64]) >>> =A0 =A0 =A0 =A0 (reg:DF 0 ax [orig:340 D.14980 ] [340])) spooles.c:291 = 106 >>> {*movdf_internal_rex64} >>> =A0 =A0 =A0(nil)) >> >> This is the original reloaded insn. >> >>> Reload 0 puts (reg/v/f:DI 182 [ b ]) in =A0(reg:DI 1 dx) for input. >>> However, reload 2 >>> puts (reg/v/f:DI 182 [ b ]) in =A0(reg:DI 1 dx) for output.without chec= king w=3D >>> hat >>> reload 0 did. >> >> Reload 2 is an optional reload which reload chose not to utilize, so this >> is not really relevant here in any case. =A0There is no output reload. >> >> The wrong code above originates from how reload 1 is handled: >> >> gen_reload is called to load the ZERO_EXTEND into (reg:DI 1). =A0This tr= iggers >> the "unary predicate" path, which recurses into gen_reload to load the o= perand >> of the ZERO_EXTEND (reg:SI 1), and subsequently generates insn 1024. >> >> The recursive call loads (plus:SI (subreg:SI (reg:DI 1)) (const_int 8)) = into >> (reg:SI 1). =A0It attempts to do that in a single SET and fails (for some >> reason). =A0It then attempts to load the constant (const_int 8) into the >> destination register (insn 1020) [** which is broken **], and re-tries. >> This still fails, so it falls through to the last attempt, which is to >> instead copy the subreg to the destination (which results in insn 1022 >> as the subreg is optimized away at this point), followed by adding the >> constant. >> >> Note that the point marked with "[** which is broken **]" is the place >> I pointed out in the previous mail. >> > > reload generates: > > (insn 914 912 0 (set (reg:SI 0 ax) > =A0 =A0 =A0 =A0(plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) > =A0 =A0 =A0 =A0 =A0 =A0(const_int 8 [0x8]))) 248 {*lea_1_x32} > =A0 =A0 (nil)) > > from > > insn =3D emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); > > Since (reg/v/f:DI 182 [ b ]) is a pseudo register, it is > rejected by > > =A0 =A0 =A0if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg)) > =A0 =A0 =A0 =A0 =A0|| (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg))) > =A0 =A0 =A0 =A0/* Base is not valid. =A0*/ > =A0 =A0 =A0 =A0return false; > > in ix86_legitimate_address_p. > Even if I added +;; Use by reload +(define_insn "*lea_0_x32" + [(set (match_operand:SI 0 "register_operand" "=3Dr") + (plus:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "Yl")))] + "TARGET_X32" + "lea{l}\t{%a1, %0|%0, %a1}" + [(set_attr "type" "lea") + (set_attr "mode" "SI")]) to generate (insn 914 912 0 (set (reg:SI 0 ax) (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) (const_int 8 [0x8]))) 248 {*lea_0_x32} (nil)) It is still rejected by constrain_operands unless I apply diff --git a/gcc/recog.c b/gcc/recog.c index 0c26c0d..358238f 100644 --- a/gcc/recog.c +++ b/gcc/recog.c @@ -2636,7 +2636,7 @@ constrain_operands (int strict) if (cl !=3D NO_REGS) { if (strict < 0 - || (strict =3D=3D 0 + || ((strict =3D=3D 0 || reload_in_progress) && REG_P (op) && REGNO (op) >=3D FIRST_PSEUDO_REGISTER) || (strict =3D=3D 0 && GET_CODE (op) =3D=3D SCRATCH) --=20 H.J.